"RFCI",
	"FCPSGN",
	"FCPSGNCC",
	"FRES",
	"FRESCC",
	"FRIM",
	"FRIMCC",
	"FRIP",
	"FRIPCC",
	"FRIZ",
	"FRIZCC",
	"FRIN",
	"FRINCC",
	"FRSQRTE",
	"FRSQRTECC",
	"FSEL",
	"FSELCC",
	"FSQRT",
	"FSQRTCC",
	"FSQRTS",
	"FSQRTSCC",
	"CNTLZD",
	"CNTLZDCC",
	"CMPW",
	"CMPWU",
	"CMPB",
	"FTDIV",
	"FTSQRT",
	"DIVD",
	"DIVDCC",
	"DIVDE",

		return op + " " + args[0] + "," + args[1] + "," + args[2]
	case SYNC:
		if args[0] == "$1" {
			return "LWSYNC"
		}
		return "HWSYNC"

	case ISEL:
		return "ISEL " + args[3] + "," + args[1] + "," + args[2] + "," + args[0]

	// store instructions always have the memory operand at the end, no need to reorder
	// indexed stores handled separately
	case STB, STBU,
		STH, STHU,

	CRXOR CR0GT, CR0EQ, CR0SO       // 4c620982

	ISEL $0, R3, R4, R5             // 7ca3201e
	ISEL $1, R3, R4, R5             // 7ca3205e
	ISEL $2, R3, R4, R5             // 7ca3209e
	ISEL $3, R3, R4, R5             // 7ca320de
	ISEL $4, R3, R4, R5             // 7ca3211e
	ISEL $31, R3, R4, R5            // 7ca327de
	ISEL CR0LT, R3, R4, R5          // 7ca3201e
	ISEL CR0GT, R3, R4, R5          // 7ca3205e

	FNMSUBS:        "fnmsubs",
	FNMSUBSCC:      "fnmsubs.",
	FRES:           "fres",
	FRESCC:         "fres.",
	FRSQRTE:        "frsqrte",
	FRSQRTECC:      "frsqrte.",
	FSEL:           "fsel",
	FSELCC:         "fsel.",
	FSQRTS:         "fsqrts",
	FSQRTSCC:       "fsqrts.",
	FSUBS:          "fsubs",
	FSUBSCC:        "fsubs.",
	ICBI:           "icbi",
	LD:             "ld",

	}

	return nil
}

// fseBaselineEntry is an entry in an FSE baseline table.
// We use these for literal/match/length values.
// Those require mapping the symbol to a baseline value,
// and then reading zero or more bits and adding the value to the baseline.
// Rather than looking these up in separate tables,
// we convert the FSE table to an FSE baseline table.
type fseBaselineEntry struct {

func cmovint(c int) int {
	x := c + 4
	if x < 0 {
		x = 182
	}
	// amd64:"CMOVQLT"
	// arm64:"CSEL\tLT"
	// ppc64x:"ISEL\t[$]0"
	// wasm:"Select"
	return x
}

func cmovchan(x, y chan int) chan int {
	if x != y {
		x = y
	}
	// amd64:"CMOVQNE"
	// arm64:"CSEL\tNE"
	// ppc64x:"ISEL\t[$]2"
	// wasm:"Select"
	return x
}

func cmovuintptr(x, y uintptr) uintptr {
	if x < y {
		x = -y

		r1 = val64 >> shift
	}
	if shift >= 0 && shift < 32 {
		// arm64:"LSR",-"CSEL"
		r2 = val32 >> shift
	}
	if shift >= 0 && shift < 16 {
		// arm64:"LSR",-"CSEL"
		r3 = val16 >> shift
	}
	if shift >= 0 && shift < 8 {
		// arm64:"LSR",-"CSEL"
		r4 = val8 >> shift
	}
	return r1, r2, r3, r4
}

	LXVD2X (P2ptr+R16), X2L
	LXVD2X (P2ptr+R17), Y2H
	LXVD2X (P2ptr+R18), Y2L
	LXVD2X (P2ptr+R19), Z2H
	LXVD2X (P2ptr+R20), Z2L

	VSEL X1H, X2H, SEL, X1H
	VSEL X1L, X2L, SEL, X1L
	VSEL Y1H, Y2H, SEL, Y1H
	VSEL Y1L, Y2L, SEL, Y1L
	VSEL Z1H, Z2H, SEL, Z1H
	VSEL Z1L, Z2L, SEL, Z1L

	STXVD2X X1H, (P3ptr+R0)
	STXVD2X X1L, (P3ptr+R16)
	STXVD2X Y1H, (P3ptr+R17)
	STXVD2X Y1L, (P3ptr+R18)
	STXVD2X Z1H, (P3ptr+R19)

// only as long as required to hold the tag with the largest index i. Consequently,
// if no field has a tag, tags may be nil.
func NewStruct(fields []*Var, tags []string) *Struct {
	var fset objset
	for _, f := range fields {
		if f.name != "_" && fset.insert(f) != nil {
			panic("multiple fields with the same name")
		}
	}
	if len(tags) > len(fields) {
		panic("more tags than fields")
	}
	s := &Struct{fields: fields, tags: tags}

		LDP.P	16(b_ptr), (acc0, acc1)
		CSEL	EQ, acc0, x0, x0
		CSEL	EQ, acc1, x1, x1
		LDP.P	16(b_ptr), (acc2, acc3)
		CSEL	EQ, acc2, x2, x2
		CSEL	EQ, acc3, x3, x3
		LDP.P	16(b_ptr), (acc4, acc5)
		CSEL	EQ, acc4, y0, y0
		CSEL	EQ, acc5, y1, y1
		LDP.P	16(b_ptr), (acc6, acc7)
		CSEL	EQ, acc6, y2, y2
		CSEL	EQ, acc7, y3, y3
		LDP.P	16(b_ptr), (acc0, acc1)
		CSEL	EQ, acc0, t0, t0
		CSEL	EQ, acc1, t1, t1