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Results 1 - 9 of 9 for CMOVQNE (0.15 sec)
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test/codegen/condmove.go
func cmovfloateq(x, y float64) int { a := 128 if x == y { a = 256 } // amd64:"CMOVQNE","CMOVQPC" // arm64:"CSEL\tEQ" // ppc64x:"ISEL\t[$]2" // wasm:"Select" return a } func cmovfloatne(x, y float64) int { a := 128 if x != y { a = 256 } // amd64:"CMOVQNE","CMOVQPS" // arm64:"CSEL\tNE" // ppc64x:"ISEL\t[$]2" // wasm:"Select" return a } //go:noinline
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Oct 06 20:57:33 UTC 2023 - 6.2K bytes - Viewed (0) -
test/codegen/bmi.go
} func isNotPowerOfTwoSelect64(x, a, b int64) int64 { var r int64 // amd64/v3:"BLSRQ",-"TESTQ",-"CALL" if isNotPowerOfTwo64(x) { r = a } else { r = b } // amd64/v3:"CMOVQNE",-"TESTQ",-"CALL" return r * 2 // force return blocks joining } func isNotPowerOfTwoSelect32(x, a, b int32) int32 { var r int32 // amd64/v3:"BLSRL",-"TESTL",-"CALL" if isNotPowerOfTwo32(x) { r = a
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jan 20 04:58:59 UTC 2023 - 4.2K bytes - Viewed (0) -
src/crypto/internal/nistec/p256_asm_amd64.s
MOVQ acc3, t3 // Add in case the operand was > p256 ADDQ $-1, acc0 ADCQ p256const0<>(SB), acc1 ADCQ $0, acc2 ADCQ p256const1<>(SB), acc3 ADCQ $0, mul0 CMOVQNE t0, acc0 CMOVQNE t1, acc1 CMOVQNE t2, acc2 CMOVQNE t3, acc3 // If condition is 0, keep original value TESTQ DX, DX CMOVQEQ acc4, acc0 CMOVQEQ acc5, acc1 CMOVQEQ acc6, acc2 CMOVQEQ acc7, acc3 // Store result
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 39.8K bytes - Viewed (0) -
src/cmd/internal/obj/x86/anames.go
"CMOVLOS", "CMOVLPC", "CMOVLPL", "CMOVLPS", "CMOVQCC", "CMOVQCS", "CMOVQEQ", "CMOVQGE", "CMOVQGT", "CMOVQHI", "CMOVQLE", "CMOVQLS", "CMOVQLT", "CMOVQMI", "CMOVQNE", "CMOVQOC", "CMOVQOS", "CMOVQPC", "CMOVQPL", "CMOVQPS", "CMOVWCC", "CMOVWCS", "CMOVWEQ", "CMOVWGE", "CMOVWGT", "CMOVWHI", "CMOVWLE", "CMOVWLS", "CMOVWLT",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 11 18:32:50 UTC 2023 - 19.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
// CMOV instructions: 64, 32 and 16-bit sizes. // if arg2 encodes a true result, return arg1, else arg0 {name: "CMOVQEQ", argLength: 3, reg: gp21, asm: "CMOVQEQ", resultInArg0: true}, {name: "CMOVQNE", argLength: 3, reg: gp21, asm: "CMOVQNE", resultInArg0: true}, {name: "CMOVQLT", argLength: 3, reg: gp21, asm: "CMOVQLT", resultInArg0: true}, {name: "CMOVQGT", argLength: 3, reg: gp21, asm: "CMOVQGT", resultInArg0: true},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Aug 04 16:40:24 UTC 2023 - 98K bytes - Viewed (1) -
src/cmd/compile/internal/ssa/_gen/AMD64.rules
(SETNE (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s)) => (SETNE (Select1 <types.TypeFlags> blsr)) (CMOVQNE x y (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s)) => (CMOVQNE x y (Select1 <types.TypeFlags> blsr)) (CMOVLNE x y (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s)) => (CMOVLNE x y (Select1 <types.TypeFlags> blsr))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 93.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64enc.s
CMOVLNE R11, R11 // 450f45db CMOVQNE (BX), DX // 480f4513 CMOVQNE (R11), DX // 490f4513 CMOVQNE DX, DX // 480f45d2 CMOVQNE R11, DX // 490f45d3 CMOVQNE (BX), R11 // 4c0f451b CMOVQNE (R11), R11 // 4d0f451b CMOVQNE DX, R11 // 4c0f45da
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Oct 08 21:38:44 UTC 2021 - 581.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteAMD64.go
v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMOVQNE x y (InvertFlags cond)) // result: (CMOVQNE x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVQNE) v.AddArg3(x, y, cond) return true } // match: (CMOVQNE y _ (FlagEQ)) // result: y for { y := v_0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 712.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
}, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQNE", argLen: 3, resultInArg0: true, asm: x86.ACMOVQNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)