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src/cmd/asm/internal/asm/operand_test.go
{"_seek<>(SB)", "_seek<>(SB)"}, {"a2+16(FP)", "a2+16(FP)"}, {"addr2+24(FP)", "addr2+24(FP)"}, {"asmcgocall<>(SB)", "asmcgocall<>(SB)"}, {"b+24(FP)", "b+24(FP)"}, {"b_len+32(FP)", "b_len+32(FP)"}, {"racecall<>(SB)", "racecall<>(SB)"}, {"rcv_name+20(FP)", "rcv_name+20(FP)"}, {"retoffset+28(FP)", "retoffset+28(FP)"}, {"runtime·_GetStdHandle(SB)", "runtime._GetStdHandle(SB)"},
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src/cmd/asm/internal/asm/testdata/loong64enc3.s
MOVW y+65540(FP), R4 // 1e020014de8f1000c4338028 MOVWU y+65540(FP), R4 // 1e020014de8f1000c433802a MOVV y+65540(FP), R4 // 1e020014de8f1000c433c028 MOVB y+65540(FP), R4 // 1e020014de8f1000c4330028 MOVBU y+65540(FP), R4 // 1e020014de8f1000c433002a MOVW y+4097(FP), R4 // 3e000014de8f1000c4278028 MOVWU y+4097(FP), R4 // 3e000014de8f1000c427802a MOVV y+4097(FP), R4 // 3e000014de8f1000c427c028
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Sat May 14 23:57:43 GMT 2022 - 6.3K bytes - Viewed (0) -
src/cmd/asm/internal/arch/arch.go
// Create maps for easy lookup of instruction names etc. for i, s := range x86.Register { register[s] = int16(i + x86.REG_AL) } // Pseudo-registers. register["SB"] = RSB register["FP"] = RFP register["PC"] = RPC if linkArch == &x86.Linkamd64 { // Alias g to R14 register["g"] = x86.REGG } // Register prefix not used on this architecture. instructions := make(map[string]obj.As)
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Mar 21 06:51:28 GMT 2023 - 21.3K bytes - Viewed (0) -
doc/asm.html
at the beginning, as in <code>first_arg+0(FP)</code> and <code>second_arg+8(FP)</code>. (The meaning of the offset—offset from the frame pointer—distinct from its use with <code>SB</code>, where it is an offset from the symbol.) The assembler enforces this convention, rejecting plain <code>0(FP)</code> and <code>8(FP)</code>. The actual name is semantically irrelevant but should be used to document
HTML - Registered: Tue May 07 11:14:38 GMT 2024 - Last Modified: Tue Nov 28 19:15:27 GMT 2023 - 36.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/loong64enc1.s
MOVVF F4, F5 // 85181d01 MOVF F4, F5 // 85941401 MOVD F4, F5 // 85981401 MOVW R4, result+16(FP) // 64608029 MOVWU R4, result+16(FP) // 64608029 MOVV R4, result+16(FP) // 6460c029 MOVB R4, result+16(FP) // 64600029 MOVBU R4, result+16(FP) // 64600029 MOVWL R4, result+16(FP) // 6460002f MOVVL R4, result+16(FP) // 6460802f MOVW R4, 1(R5) // a4048029 MOVWU R4, 1(R5) // a4048029 MOVV R4, 1(R5) // a404c029
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Mar 31 02:56:19 GMT 2023 - 6.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/parse.go
} p.get(')') a.Type = obj.TYPE_MEM if r1 < 0 { // Pseudo-register reference. if r2 != 0 { p.errorf("cannot use pseudo-register in pair") return } // For SB, SP, and FP, there must be a name here. 0(FP) is not legal. if name != "PC" && a.Name == obj.NAME_NONE { p.errorf("cannot reference %s without a symbol", name) } p.setPseudoRegister(a, name, false, prefix) return } a.Reg = r1
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Feb 21 14:34:57 GMT 2024 - 36.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64error.s
// Pseudo-registers should not be used as scaled index. CALL (AX)(PC*1) // ERROR "invalid instruction" CALL (AX)(SB*1) // ERROR "invalid instruction" CALL (AX)(FP*1) // ERROR "invalid instruction" // Forbid memory operands for MOV CR/DR. See #24981. MOVQ CR0, (AX) // ERROR "invalid instruction" MOVQ CR2, (AX) // ERROR "invalid instruction"
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Jun 14 00:03:57 GMT 2023 - 8.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips.s
// // special // SYSCALL BREAK SYNC // // conditional move on zero/nonzero gp value // CMOVN R1, R2, R3 CMOVZ R1, R2, R3 // // conditional move on fp false/true // CMOVF R1, R2 CMOVT R1, R2 // // conditional traps // TEQ $1, R1, R2 TEQ $1, R1 // // other // CLO R1, R2 SQRTD F0, F1
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Aug 08 12:17:12 GMT 2023 - 6.7K bytes - Viewed (0) -
doc/go1.17_spec.html
0. 72.40 072.40 // == 72.40 2.71828 1.e+0 6.67428e-11 1E6 .25 .12345E+5 1_5. // == 15.0 0.15e+0_2 // == 15.0 0x1p-2 // == 0.25 0x2.p10 // == 2048.0 0x1.Fp+0 // == 1.9375 0X.8p-0 // == 0.5 0X_1FFFP-16 // == 0.1249847412109375 0x15e-2 // == 0x15e - 2 (integer subtraction) 0x.p1 // invalid: mantissa has no digits
HTML - Registered: Tue May 07 11:14:38 GMT 2024 - Last Modified: Thu Apr 11 20:22:45 GMT 2024 - 211.6K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64.s
MOVWBR (R3), R5 // 7ca01c2c MOVHBR (R3)(R4), R5 // 7ca41e2c MOVHBR (R3)(R0), R5 // 7ca01e2c MOVHBR (R3), R5 // 7ca01e2c OR $0, R0, R0 MOVD $foo+4009806848(FP), R5 // 3ca1ef0138a5cc40 or 0600ef0038a1cc40 MOVD $foo(SB), R5 // 3ca0000038a50000 or 0610000038a00000 MOVDU 8(R3), R4 // e8830009 MOVDU (R3)(R4), R5 // 7ca4186a
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Apr 24 15:53:25 GMT 2024 - 49K bytes - Viewed (0)