VSCATTERPF0DPD K5, (SP)(Y4*2)                      // 62f2fd4dc62c64
	VSCATTERPF0DPD K5, (DX)(Y10*4)                     // 62b2fd4dc62c92
	VSCATTERPF0DPS K3, (DX)(Z10*4)                     // 62b27d4bc62c92
	VSCATTERPF0DPS K3, (AX)(Z4*1)                      // 62f27d4bc62c20
	VSCATTERPF0DPS K3, (SP)(Z4*2)                      // 62f27d4bc62c64
	VSCATTERPF0QPD K4, (DX)(Z10*4)                     // 62b2fd4cc72c92

	V4FNMADDPS 99(R15)(R15*1), [Z1-Z4], K3, Z15        // 6212774baabc3f63000000
	V4FNMADDPS (DX), [Z1-Z4], K3, Z15                  // 6272774baa3a
	V4FNMADDPS 99(R15)(R15*1), [Z11-Z14], K3, Z15      // 6212274baabc3f63000000
	V4FNMADDPS (DX), [Z11-Z14], K3, Z15                // 6272274baa3a
	V4FNMADDPS 99(R15)(R15*1), [Z21-Z24], K3, Z15      // 62125743aabc3f63000000
	V4FNMADDPS (DX), [Z21-Z24], K3, Z15                // 62725743aa3a

	VP4DPWSSD 15(DX)(BX*8), [Z2-Z5], K4, Z17           // 62e26f4c528cda0f000000
	VP4DPWSSD 7(SI)(DI*1), [Z12-Z15], K4, Z17          // 62e21f4c528c3e07000000
	VP4DPWSSD 15(DX)(BX*8), [Z12-Z15], K4, Z17         // 62e21f4c528cda0f000000
	VP4DPWSSD 7(SI)(DI*1), [Z22-Z25], K4, Z17          // 62e24f44528c3e07000000
	VP4DPWSSD 15(DX)(BX*8), [Z22-Z25], K4, Z17         // 62e24f44528cda0f000000

	ADDL -2147483648(AX), AX // 038000000080
	// Make sure MOV CR/DR continues to work after changing its movtabs.
	MOVL CR0, AX // 0f20c0
	MOVL CR0, DX // 0f20c2
	MOVL CR4, DI // 0f20e7
	MOVL AX, CR0 // 0f22c0
	MOVL DX, CR0 // 0f22c2
	MOVL DI, CR4 // 0f22e7
	MOVL DR0, AX // 0f21c0
	MOVL DR6, DX // 0f21f2
	MOVL DR7, SI // 0f21fe
	// Test other movtab entries.
	PUSHL SS // 16
	PUSHL FS // 0fa0
	POPL FS  // 0fa1
	POPL SS  // 17

	VPCLMULQDQ $97, 15(DX)(BX*8), Z26, Z24             // 62632d404484da0f00000061 or 6263ad404484da0f00000061
	VPCLMULQDQ $97, Z9, Z0, Z12                        // 62537d4844e161 or 6253fd4844e161
	VPCLMULQDQ $97, Z3, Z0, Z12                        // 62737d4844e361 or 6273fd4844e361
	VPCLMULQDQ $97, 7(SI)(DI*1), Z0, Z12               // 62737d4844a43e0700000061 or 6273fd4844a43e0700000061

// LTYPEM spec6	{ outcode($1, &$2); }
	MOVL	AX, R11
	MOVL	$4, R11
//	MOVL	AX, 0(AX):DS // no longer works - did it ever?

// LTYPEI spec7	{ outcode($1, &$2); }
	IMULB	DX
	IMULW	DX, BX
	IMULL	R11, R12
	IMULQ	foo+4(SB), R11

// LTYPEXC spec8	{ outcode($1, &$2); }
	CMPPD	X1, X2, 4
	CMPPD	foo+4(SB), X2, 4

// LTYPEX spec9	{ outcode($1, &$2); }
	PINSRW	$4, AX, X2

		lines(
			"#define LOAD(off, reg) \\",
			"\tMOVBLZX	(off*4)(R12),	reg \\",
			"\tADDB	reg,		DX",
			"",
			"LOAD(8, AX)",
		),
		"\n.\n.MOVBLZX.(.8.*.4.).(.R12.).,.AX.\n.ADDB.AX.,.DX.\n",
	},
	{
		"nested multiline macro",
		lines(
			"#define KEYROUND(xmm, load, off, r1, r2, index) \\",
			"\tMOVBLZX	(BP)(DX*4),	R8 \\",
			"\tload((off+1), r2) \\",
			"\tMOVB	R8,		(off*4)(R12) \\",

	VPOPCNTQ 15(DX), K4, X23                           // 62e2fd0c55ba0f000000
	VPOPCNTQ X24, K4, X11                              // 6212fd0c55d8
	VPOPCNTQ X14, K4, X11                              // 6252fd0c55de
	VPOPCNTQ X0, K4, X11                               // 6272fd0c55d8
	VPOPCNTQ 99(R15)(R15*4), K4, X11                   // 6212fd0c559cbf63000000

		{"VADDPD.SAE.SAE X0, X1, X2", `duplicate suffix "SAE"`},
		{"VADDPD.RZ_SAE.SAE X0, X1, X2", `bad suffix combination`},

		// BSWAP on 16-bit registers is undefined. See #29167,
		{"BSWAPW DX", `unrecognized instruction`},
		{"BSWAPW R11", `unrecognized instruction`},
	})
}

func testBadInstParser(t *testing.T, goarch string, tests []badInstTest) {
	for i, test := range tests {

	PINSRD	$1, (AX), X0
	PINSRD	$2, foo+4(FP), X0

// Was bug: LOOP is a branch instruction.
	JCS	2(PC)
loop:
	LOOP	loop // LOOP

// Tests for TLS reference.
	MOVL    (TLS), AX
	MOVL    8(TLS), DX

// LTYPE0 nonnon	{ outcode(int($1), &$2); }
	RET