// LTYPEX spec10	{ outcode(int($1), &$2); }
	PINSRD	$1, (AX), X0
	PINSRD	$2, foo+4(FP), X0

// Was bug: LOOP is a branch instruction.
	JCS	2(PC)
loop:
	LOOP	loop // LOOP

// Tests for TLS reference.
	MOVL    (TLS), AX
	MOVL    8(TLS), DX

// LTYPE0 nonnon	{ outcode(int($1), &$2); }
	RET

	MOVW	foo+32323(SP)(AX*1), DX		// 668b9404437e0000
	MOVB	foo(SP)(AX*2), AL		// 8a0444
	MOVB	foo+32(SP)(CX*4), AH		// 8a648c20
	MOVB	foo+32323(SP)(CX*8), R9		// 448a8ccc437e0000

// Tests for TLS reference.
	MOVQ	(TLS), AX
	MOVQ	8(TLS), DX

// LTYPE0 nonnon	{ outcode($1, &$2); }
	RET // c3

	// TODO(quasilyte): improve error message (#21860).
	VPGATHERQQ X2, (BP)(X20*2), X3  // ERROR "invalid instruction"
	VPGATHERQQ Y2, (BP)(Y20*2), Y3  // ERROR "invalid instruction"
	// YzrMulti4 expects exactly 4 registers referenced by REG_LIST.
	// TODO(quasilyte): improve error message (#21860).
	V4FMADDPS (AX), [Z0-Z4], K1, Z7  // ERROR "invalid instruction"
	V4FMADDPS (AX), [Z0-Z0], K1, Z7  // ERROR "invalid instruction"