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Results 1 - 10 of 15 for RLDICR (0.12 sec)
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test/codegen/shift.go
// ppc64x:-".*RLWINM",-".*RLDICR",".*CLRLSLDI" f := tab[byte(v)^b] // ppc64x:-".*RLWINM",-".*RLDICR",".*CLRLSLDI" f += tab[byte(v)&b] // ppc64x:-".*RLWINM",-".*RLDICR",".*CLRLSLDI" f += tab[byte(v)|b] // ppc64x:-".*RLWINM",-".*RLDICR",".*CLRLSLDI" f += tab[uint16(v)&h] // ppc64x:-".*RLWINM",-".*RLDICR",".*CLRLSLDI" f += tab[uint16(v)^h]
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue May 21 18:53:43 UTC 2024 - 12.7K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/anames.go
"MULHDU", "MULHDUCC", "MULLD", "MULLDCC", "MULLDVCC", "MULLDV", "RFID", "RLDMI", "RLDMICC", "RLDIMI", "RLDIMICC", "RLDC", "RLDCCC", "RLDCR", "RLDCRCC", "RLDICR", "RLDICRCC", "RLDCL", "RLDCLCC", "RLDICL", "RLDICLCC", "RLDIC", "RLDICCC", "CLRLSLDI", "ROTL", "ROTLW", "SLBIA", "SLBIE", "SLBMFEE", "SLBMFEV", "SLBMTE",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 6.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64latelower.rules
// Convert simple bit masks to an equivalent rldic[lr] if possible. (AND x:(MOVDconst [m]) n) && isPPC64ValidShiftMask(m) => (RLDICL [encodePPC64RotateMask(0,m,64)] n) (AND x:(MOVDconst [m]) n) && m != 0 && isPPC64ValidShiftMask(^m) => (RLDICR [encodePPC64RotateMask(0,m,64)] n) // If the RLDICL does not rotate its value, a shifted value can be merged. (RLDICL [em] x:(SRDconst [s] a)) && (em&0xFF0000) == 0 => (RLDICL [mergePPC64RLDICLandSRDconst(em, s)] a)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 3.8K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/doc.go
More recently, Go opcodes were added which map directly onto the PPC64 opcodes. It is recommended to use the newer opcodes to avoid confusion. RLDICL $0,R4,$15,R6 => rldicl r6,r4,0,15 RLDICR $0,R4,$15,R6 => rldicr r6.r4,0,15 # Register naming 1. Special register usage in Go asm The following registers should not be modified by user Go assembler code.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Apr 21 16:47:45 UTC 2023 - 11.3K bytes - Viewed (0) -
src/runtime/sys_linux_ppc64x.s
MOVD m_curg(R21), R6 CMP g, R6 BNE noswitch MOVD m_g0(R21), R7 MOVD (g_sched+gobuf_sp)(R7), R1 // Set SP to g0 stack noswitch: SUB $16, R1 // Space for results RLDICR $0, R1, $59, R1 // Align for C code MOVD R12, CTR MOVD R1, R4 // Store g on gsignal's stack, so if we receive a signal // during VDSO code we can find the g.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 18:17:17 UTC 2024 - 18.1K bytes - Viewed (0) -
src/internal/bytealg/index_ppc64x.s
loadge16: ANDCC $15, R5, R9 // Find byte offset of sep ADD R9, R6, R10 // Add sep len CMP R10, $16 // Check if sep len+offset > 16 BGT sepcross16 // Sep crosses 16 byte boundary RLDICR $0, R5, $59, R8 // Adjust addr to 16 byte container VLOADSWAP(R8, R0, V0, V0) // Load 16 bytes @R8 into V0 SLD $3, R9 // Set up shift count for VSLO MTVSRD R9, V8 // Set up shift count for VSLO
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Apr 21 16:47:45 UTC 2023 - 31.6K bytes - Viewed (0) -
src/internal/bytealg/indexbyte_ppc64x.s
BLT cmp16 // Jump to the small string case if it's <32 bytes. CMP R4,$64,CR1 MOVD $16,R11 MOVD R3,R8 BLT CR1,cmp32 // Special case for length 32 - 63 MOVD $32,R12 MOVD $48,R6 RLDICR $0,R4,$63-6,R9 // R9 = len &^ 63 ADD R3,R9,R9 // R9 = &s[len &^ 63] ANDCC $63,R4 // (len &= 63) cmp 0. PCALIGN $16 loop64: LXVD2X (R0)(R8),V2 // Scan 64 bytes at a time, starting at &s[0] VCMPEQUBCC V2,V1,V6
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Apr 21 16:10:29 UTC 2023 - 6.3K bytes - Viewed (0) -
test/codegen/bits.go
return } // Verify rotate and mask instructions, and further simplified instructions for small types func bitRotateAndMask(io64 [8]uint64, io32 [4]uint32, io16 [4]uint16, io8 [4]uint8) { // ppc64x: "RLDICR\t[$]0, R[0-9]*, [$]47, R" io64[0] = io64[0] & 0xFFFFFFFFFFFF0000 // ppc64x: "RLDICL\t[$]0, R[0-9]*, [$]16, R" io64[1] = io64[1] & 0x0000FFFFFFFFFFFF // ppc64x: -"SRD", -"AND", "RLDICL\t[$]60, R[0-9]*, [$]16, R"
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 7.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewritePPC64latelower.go
v.AuxInt = int64ToAuxInt(encodePPC64RotateMask(0, m, 64)) v.AddArg(n) return true } break } // match: (AND x:(MOVDconst [m]) n) // cond: m != 0 && isPPC64ValidShiftMask(^m) // result: (RLDICR [encodePPC64RotateMask(0,m,64)] n) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if x.Op != OpPPC64MOVDconst { continue } m := auxIntToInt64(x.AuxInt)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 16.5K bytes - Viewed (0) -
src/hash/crc32/crc32_ppc64le.s
#else VSLDOI $4,V8,zeroes,V8 #endif #ifdef BYTESWAP_DATA MOVD $·byteswapcons(SB),R3 LVX (R3),byteswap #endif CMPU R5,$256 // length of bytes BLT short RLDICR $0,R5,$56,R6 // chunk to process // First step for larger sizes l1: MOVD $32768,R7 MOVD R7,R9 CMP R6,R7 // compare R6, R7 (MAX SIZE) BGT top // less than MAX, just do remainder MOVD R6,R7 top:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 06 12:09:50 UTC 2024 - 13.1K bytes - Viewed (0)