(CMPconst <t> [0] (Select0 z:((ADDCCconst|ANDCCconst|NEGCC|CNTLZDCC|RLDICLCC) y))) => (Select1 <t> z)

// After trying to convert ANDconst to ANDCCconst above, if the CC result is not needed, try to avoid using
// ANDconst which clobbers CC.
(ANDconst [m] x) && isPPC64ValidShiftMask(m) => (RLDICL [encodePPC64RotateMask(0,m,64)] x)

// Likewise, trying converting RLDICLCC back to ANDCCconst as it is faster.

	"MULLDV",
	"RFID",
	"RLDMI",
	"RLDMICC",
	"RLDIMI",
	"RLDIMICC",
	"RLDC",
	"RLDCCC",
	"RLDCR",
	"RLDCRCC",
	"RLDICR",
	"RLDICRCC",
	"RLDCL",
	"RLDCLCC",
	"RLDICL",
	"RLDICLCC",
	"RLDIC",
	"RLDICCC",
	"CLRLSLDI",
	"ROTL",
	"ROTLW",
	"SLBIA",
	"SLBIE",
	"SLBMFEE",
	"SLBMFEV",
	"SLBMTE",
	"SLD",
	"SLDCC",
	"SRD",
	"SRAD",
	"SRADCC",

			break
		}
		z := v_0.Args[0]
		if z.Op != OpPPC64CNTLZDCC {
			break
		}
		v.reset(OpSelect1)
		v.Type = t
		v.AddArg(z)
		return true
	}
	// match: (CMPconst <t> [0] (Select0 z:(RLDICLCC y)))
	// result: (Select1 <t> z)
	for {
		t := v.Type
		if auxIntToInt64(v.AuxInt) != 0 || v_0.Op != OpSelect0 {
			break
		}
		z := v_0.Args[0]
		if z.Op != OpPPC64RLDICLCC {
			break
		}

		{name: "RLDICL", argLength: 1, reg: gp11, asm: "RLDICL", aux: "Int64"},                          // Auxint is encoded similarly to RLWINM, but only MB and SH are valid. ME is always 63.
		{name: "RLDICLCC", argLength: 1, reg: gp11, asm: "RLDICLCC", aux: "Int64", typ: "(Int, Flags)"}, // Auxint is encoded similarly to RLWINM, but only MB and SH are valid. ME is always 63. Sets CC.

	RLDCLCC $0, R4, $15, R6         // 78860721
	RLDCR $0, R4, $-16, R6          // 788606f2
	RLDCRCC $0, R4, $-16, R6        // 788606f3
	RLDICL $0, R4, $15, R6          // 788603c0
	RLDICLCC $0, R4, $15, R6        // 788603c1
	RLDICR $0, R4, $15, R6          // 788603c4
	RLDICRCC $0, R4, $15, R6        // 788603c5
	RLDIC $0, R4, $15, R6           // 788603c8
	RLDICCC $0, R4, $15, R6         // 788603c9

	MULHDUCC
	MULHW
	MULHWCC
	MULHWU
	MULHWUCC
	MULLD
	MULLDCC
	MULLDO
	MULLDOCC
	RFID
	RLDCL
	RLDCLCC
	RLDCR
	RLDCRCC
	RLDIC
	RLDICCC
	RLDICL
	RLDICLCC
	RLDICR
	RLDICRCC
	RLDIMI
	RLDIMICC
	SC
	SLBIA
	SLBIE
	SLD
	SLDCC
	SRAD
	SRADCC
	SRADI
	SRADICC
	SRD
	SRDCC
	STD
	STDCXCC
	STDU

			},
			outputs: []outputInfo{
				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "RLDICLCC",
		auxType: auxInt64,
		argLen:  1,
		asm:     ppc64.ARLDICLCC,
		reg: regInfo{
			inputs: []inputInfo{