// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

// Issue 11987. The ppc64 SRADCC instruction was misassembled in a way
// lost bit 5 of the immediate so v>>32 was assembled as v>>0.  SRADCC
// is only ever inserted by peep so it's hard to be sure when it will
// be used. This formulation worked when the bug was fixed.

package main

import "fmt"

	"RLDICLCC",
	"RLDIC",
	"RLDICCC",
	"CLRLSLDI",
	"ROTL",
	"ROTLW",
	"SLBIA",
	"SLBIE",
	"SLBMFEE",
	"SLBMFEV",
	"SLBMTE",
	"SLD",
	"SLDCC",
	"SRD",
	"SRAD",
	"SRADCC",
	"SRDCC",
	"EXTSWSLI",
	"EXTSWSLICC",
	"STDCCC",
	"TD",
	"SETB",
	"DWORD",
	"REMD",
	"REMDU",
	"HRFID",
	"POPCNTD",
	"POPCNTW",
	"POPCNTB",
	"CNTTZW",
	"CNTTZWCC",

		return true
	case OR, ORCC, ORC, ORCCC, AND, ANDCC, ANDC, ANDCCC, XOR, XORCC, NAND, NANDCC, EQV, EQVCC, NOR, NORCC:
		return true
	case SLW, SLWCC, SLD, SLDCC, SRW, SRAW, SRWCC, SRAWCC, SRD, SRDCC, SRAD, SRADCC:
		return true
	}
	return false
}

// revCondMap maps a conditional register bit to its inverse, if possible.
var revCondMap = map[string]string{
	"LT": "GE", "GT": "LE", "EQ": "NE",
}

	RLDCL
	RLDCLCC
	RLDCR
	RLDCRCC
	RLDIC
	RLDICCC
	RLDICL
	RLDICLCC
	RLDICR
	RLDICRCC
	RLDIMI
	RLDIMICC
	SC
	SLBIA
	SLBIE
	SLD
	SLDCC
	SRAD
	SRADCC
	SRADI
	SRADICC
	SRD
	SRDCC
	STD
	STDCXCC
	STDU
	STDUX
	STDX
	STFIWX
	STWCXCC
	SUBF
	SUBFCC
	SUBFO
	SUBFOCC
	TD
	TDI
	TLBSYNC