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Results 1 - 6 of 6 for STDCCC (0.13 sec)

  1. src/internal/runtime/atomic/atomic_ppc64x.s

    	MOVD	val+8(FP), R4
    	LWSYNC
    again:
    	LDAR	(R3), R6
    	OR	R4, R6, R7
    	STDCCC	R7, (R3)
    	BNE	again
    	MOVD	R6, ret+16(FP)
    	RET
    
    // func And64(addr *uint64, v uint64) old uint64
    TEXT ·And64(SB), NOSPLIT, $0-24
    	MOVD	ptr+0(FP), R3
    	MOVD	val+8(FP), R4
    	LWSYNC
    again:
    	LDAR	(R3),R6
    	AND	R4, R6, R7
    	STDCCC	R7, (R3)
    	BNE	again
    	MOVD	R6, ret+16(FP)
    	RET
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 25 19:53:03 UTC 2024
    - 7.5K bytes
    - Viewed (0)
  2. src/cmd/internal/obj/ppc64/anames.go

    	"ROTL",
    	"ROTLW",
    	"SLBIA",
    	"SLBIE",
    	"SLBMFEE",
    	"SLBMFEV",
    	"SLBMTE",
    	"SLD",
    	"SLDCC",
    	"SRD",
    	"SRAD",
    	"SRADCC",
    	"SRDCC",
    	"EXTSWSLI",
    	"EXTSWSLICC",
    	"STDCCC",
    	"TD",
    	"SETB",
    	"DWORD",
    	"REMD",
    	"REMDU",
    	"HRFID",
    	"POPCNTD",
    	"POPCNTW",
    	"POPCNTB",
    	"CNTTZW",
    	"CNTTZWCC",
    	"CNTTZD",
    	"CNTTZDCC",
    	"COPY",
    	"PASTECC",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Apr 01 18:50:29 UTC 2024
    - 6.7K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ppc64/ssa.go

    		p3.To.Type = obj.TYPE_BRANCH
    		p3.To.SetTarget(p)
    
    	case ssa.OpPPC64LoweredAtomicAdd32,
    		ssa.OpPPC64LoweredAtomicAdd64:
    		// LWSYNC
    		// LDAR/LWAR    (Rarg0), Rout
    		// ADD		Rarg1, Rout
    		// STDCCC/STWCCC Rout, (Rarg0)
    		// BNE         -3(PC)
    		// MOVW		Rout,Rout (if Add32)
    		ld := ppc64.ALDAR
    		st := ppc64.ASTDCCC
    		if v.Op == ssa.OpPPC64LoweredAtomicAdd32 {
    			ld = ppc64.ALWAR
    			st = ppc64.ASTWCCC
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 19:59:38 UTC 2024
    - 55.4K bytes
    - Viewed (0)
  4. src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go

    	DIVDOCC:   "DIVDVCC",
    	DIVDUO:    "DIVDUV",
    	DIVDUOCC:  "DIVDUVCC",
    	ADDI:      "ADD",
    	MULLI:     "MULLD",
    	SRADI:     "SRAD",
    	STBCXCC:   "STBCCC",
    	STWCXCC:   "STWCCC",
    	STDCXCC:   "STDCCC",
    	LI:        "MOVD",
    	LBZ:       "MOVBZ", STB: "MOVB",
    	LBZU: "MOVBZU", STBU: "MOVBU",
    	LHZ: "MOVHZ", LHA: "MOVH", STH: "MOVH",
    	LHZU: "MOVHZU", STHU: "MOVHU",
    	LWZ: "MOVWZ", LWA: "MOVW", STW: "MOVW",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 22 17:16:14 UTC 2022
    - 10.9K bytes
    - Viewed (0)
  5. src/cmd/asm/internal/asm/testdata/ppc64.s

    	STWCCC R3, (R4)(R5)             // 7c65212d
    	STWCCC R3, (R4)(R0)             // 7c60212d
    	STWCCC R3, (R4)                 // 7c60212d
    	STDCCC R3, (R4)(R5)             // 7c6521ad
    	STDCCC R3, (R4)(R0)             // 7c6021ad
    	STDCCC R3, (R4)                 // 7c6021ad
    	STHCCC R3, (R4)(R5)             // 7c6525ad
    	STHCCC R3, (R4)(R0)             // 7c6025ad
    	STHCCC R3, (R4)                 // 7c6025ad
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 17 21:53:50 UTC 2024
    - 50.2K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/_gen/PPC64Ops.go

    		// atomic add32, 64
    		// LWSYNC
    		// LDAR         (Rarg0), Rout
    		// ADD		Rarg1, Rout
    		// STDCCC       Rout, (Rarg0)
    		// BNE          -3(PC)
    		// return new sum
    		{name: "LoweredAtomicAdd32", argLength: 3, reg: gpxchg, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true},
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 19:59:38 UTC 2024
    - 43.8K bytes
    - Viewed (0)
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