} else {
			return fmt.Sprintf("%s.SXTB", regname(r))
		}
	case REG_SXTH <= r && r < REG_SXTW:
		if ext != 0 {
			return fmt.Sprintf("%s.SXTH<<%d", regname(r), ext)
		} else {
			return fmt.Sprintf("%s.SXTH", regname(r))
		}
	case REG_SXTW <= r && r < REG_SXTX:
		if ext != 0 {
			return fmt.Sprintf("%s.SXTW<<%d", regname(r), ext)
		} else {

				return errors.New("invalid shift for the register offset addressing mode")
			}
			a.Reg = arm64.REG_SXTH + Rnum
		case "SXTW":
			if a.Type == obj.TYPE_MEM {
				a.Index = arm64.REG_SXTW + Rnum
			} else {
				a.Reg = arm64.REG_SXTW + Rnum
			}
		case "SXTX":
			if a.Type == obj.TYPE_MEM {
				a.Index = arm64.REG_SXTX + Rnum
			} else {
				a.Reg = arm64.REG_SXTX + Rnum
			}
		case "LSL":

const REG_LSL = obj.RBaseARM64 + 1<<9
const REG_EXT = obj.RBaseARM64 + 1<<11

const (
	REG_UXTB = REG_EXT + iota<<8
	REG_UXTH
	REG_UXTW
	REG_UXTX
	REG_SXTB
	REG_SXTH
	REG_SXTW
	REG_SXTX
)

// Special registers, after subtracting obj.RBaseARM64, bit 12 indicates
// a special register and the low bits select the register.

		}
	case REG_UXTX <= r && r < REG_SXTB:
		return roff(rm, 3, num)
	case REG_SXTB <= r && r < REG_SXTH:
		return roff(rm, 4, num)
	case REG_SXTH <= r && r < REG_SXTW:
		return roff(rm, 5, num)
	case REG_SXTW <= r && r < REG_SXTX:
		if a.Type == obj.TYPE_MEM {
			if num == 0 {
				return roff(rm, 6, 2)
			} else {
				return roff(rm, 6, 6)
			}
		} else {