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src/cmd/asm/internal/asm/testdata/riscv64error.s
TEXT errors(SB),$0 MOV $errors(SB), (X5) // ERROR "address load must target register" MOV $8(SP), (X5) // ERROR "address load must target register" MOVB $8(SP), X5 // ERROR "unsupported address load" MOVH $8(SP), X5 // ERROR "unsupported address load" MOVW $8(SP), X5 // ERROR "unsupported address load" MOVF $8(SP), X5 // ERROR "unsupported address load" MOV $1234, 0(SP) // ERROR "constant load must target register"
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Sun Apr 07 03:32:27 GMT 2024 - 2.8K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64.s
JMP 4(X5) // 67804200 // CALL and JMP to symbol are encoded as JAL (using LR or ZERO // respectively), with a R_RISCV_JAL relocation. The linker resolves // the real address and updates the immediate, using a trampoline in // the case where the address is not directly reachable. CALL asmtest(SB) // ef000000 JMP asmtest(SB) // 6f000000 // Branch pseudo-instructions BEQZ X5, 2(PC) // 63840200
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Mar 22 04:42:21 GMT 2024 - 16.7K bytes - Viewed (1) -
src/cmd/asm/internal/asm/testdata/arm64.s
FMOVD 0x1006ff8(R1), F2 // FMOVD 16805880(R1), F2 // 3bfc7f9162ff7ffd // very large or unaligned offset uses constant pool. // the encoding cannot be checked as the address of the constant pool is unknown. // here we only test that they can be assembled. MOVB R1, 0x1000000(R2) // MOVB R1, 16777216(R2) MOVB R1, 0x44332211(R2) // MOVB R1, 1144201745(R2)
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Dec 08 03:28:17 GMT 2023 - 94.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64error.s
MOVL (AX)(Y0*1), AX // ERROR "invalid instruction" // VSIB/VM is invalid without vector index. // TODO(quasilyte): improve error message (#21860). // "invalid VSIB address (missing vector index)" VPGATHERQQ Y2, (BP), Y1 // ERROR "invalid instruction" // AVX2GATHER mask/index/dest #UD cases. VPGATHERQQ Y2, (BP)(X2*2), Y2 // ERROR "mask, index, and destination registers should be distinct"
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Jun 14 00:03:57 GMT 2023 - 8.9K bytes - Viewed (0)