ADRP 12(PC), R2    // 02000090

// LDP/STP
	LDP	(R0), (R0, R1)      // 000440a9
	LDP	(R0), (R1, R2)      // 010840a9
	LDP	8(R0), (R1, R2)     // 018840a9
	LDP	-8(R0), (R1, R2)    // 01887fa9
	LDP	11(R0), (R1, R2)    // 1b2c0091610b40a9
	LDP	1024(R0), (R1, R2)  // 1b001091610b40a9
	LDP.W	8(R0), (R1, R2)     // 0188c0a9
	LDP.P	8(R0), (R1, R2)     // 0188c0a8
	LDP	(RSP), (R1, R2)     // e10b40a9

	CRC32CB R19, R27, R22                      // 7653d31a
	CRC32CH R21, R0, R20                       // 1454d51a
	CRC32CW R9, R3, R21                        // 7558c91a
	CRC32CX R11, R0, R24                       // 185ccb9a
	CSELW LO, R4, R20, R12                     // 8c30941a
	CSEL GE, R0, R12, R14                      // 0ea08c9a
	CSETW GE, R3                               // e3b79f1a

	VREV16	V1.H4, V2.H4                                     // ERROR "invalid arrangement"
	FLDPQ	(R0), (R1, R2)                                   // ERROR "invalid register pair"
	FLDPQ	(R1), (F2, F2)                                   // ERROR "constrained unpredictable behavior"
	FSTPQ	(R1, R2), (R0)                                   // ERROR "invalid register pair"
	FLDPD	(R0), (R1, R2)                                   // ERROR "invalid register pair"

is in [0, 15]. func decompose32(r fieldElement) (r1 byte, r0 int32) { x := fieldFromMontgomery(r) r1 = highBits32(x) // r - r1 * (2 * γ2) mod± q r0 = int32(x) - int32(r1)*2*(q-1)/32 r0 = constantTimeSelectLe(q/2+1, r0, r0-q, r0) return r1, r0 } // useHint32 implements UseHint from FIPS 204 for γ2 = (q - 1) / 32. func useHint32(r fieldElement, hint byte) byte { const m = 16 // (q − 1) / (2 * γ2) r1, r0 := decompose32(r) if hint == 1 { if r0 > 0 { r1 = (r1 + 1) % m } else { // Underflow is safe, because...

		return 10
	}
	if name[0] != 'R' {
		p.errorf("expected g or R0 through R15; found %s", name)
		return 0
	}
	r, ok := p.registerReference(name)
	if !ok {
		return 0
	}
	reg := r - p.arch.Register["R0"]
	if reg < 0 {
		// Could happen for an architecture having other registers prefixed by R
		p.errorf("expected g or R0 through R15; found %s", name)
		return 0
	}
	return uint16(reg)
}

	ROTRV	$4, R4			// 84104d00
	SYSCALL				// 00002b00
	BEQ	R4, R5, 1(PC)		// 85040058
	BEQ	R4, 1(PC)		// 80040040
	BEQ	R4, R0, 1(PC)		// 80040040
	BEQ	R0, R4, 1(PC)		// 80040040
	BNE	R4, R5, 1(PC)		// 8504005c
	BNE	R4, 1(PC)		// 80040044
	BNE	R4, R0, 1(PC)		// 80040044
	BNE	R0, R4, 1(PC)		// 80040044
	BLTU	R4, 1(PC)		// 80040068
	MOVF	y+8(FP), F4		// 6440002b
	MOVD	y+8(FP), F4		// 6440802b

      limiter.acquire(); // #7
    }
    assertEvents(
        "R0.00, R1.38, R1.13, R0.88, R0.63, R0.50, R0.50, R0.50", // #1
        "U0.50", // #2
        "U4.00", // #3
        "R0.00, R1.38, R1.13, R0.88, R0.63, R0.50, R0.50, R0.50", // #4
        "U0.50", // #5
        "U2.00", // #6
        "R0.00, R0.50, R0.50, R0.50, R0.50, R0.50, R0.50, R0.50"); // #7
  }

  public void testWarmUpWithColdFactor() {

      limiter.acquire(); // #7
    }
    assertEvents(
        "R0.00, R1.38, R1.13, R0.88, R0.63, R0.50, R0.50, R0.50", // #1
        "U0.50", // #2
        "U4.00", // #3
        "R0.00, R1.38, R1.13, R0.88, R0.63, R0.50, R0.50, R0.50", // #4
        "U0.50", // #5
        "U2.00", // #6
        "R0.00, R0.50, R0.50, R0.50, R0.50, R0.50, R0.50, R0.50"); // #7
  }

  public void testWarmUpWithColdFactor() {

			p.toPatch = append(p.toPatch, Patch{targetAddr, target.Sym.Name})
		} else {
			p.branch(targetAddr, targetProg)
		}
	case target.Type == obj.TYPE_MEM && target.Name == obj.NAME_NONE:
		// JMP 4(R0)
		*targetAddr = *target
		// On the ppc64, 9a encodes BR (CTR) as BR CTR. We do the same.
		if p.arch.Family == sys.PPC64 && target.Offset == 0 {
			targetAddr.Type = obj.TYPE_REG
		}