switch op {
	case ppc64.AADDMECC, ppc64.AADDMEVCC, ppc64.AADDMEV, ppc64.AADDME,
		ppc64.AADDZECC, ppc64.AADDZEVCC, ppc64.AADDZEV, ppc64.AADDZE,
		ppc64.ACNTLZDCC, ppc64.ACNTLZD, ppc64.ACNTLZWCC, ppc64.ACNTLZW,
		ppc64.AEXTSBCC, ppc64.AEXTSB, ppc64.AEXTSHCC, ppc64.AEXTSH,
		ppc64.AEXTSWCC, ppc64.AEXTSW, ppc64.ANEGCC, ppc64.ANEGVCC,
		ppc64.ANEGV, ppc64.ANEG, ppc64.ASLBMFEE, ppc64.ASLBMFEV,

// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

// This contains the majority of valid opcode combinations
// available in cmd/internal/obj/ppc64/asm9.go with
// their valid instruction encodings.

#include "../../../../../runtime/textflag.h"

// In case of index mode instructions, usage of
// (Rx)(R0) is equivalent to (Rx+R0)

// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

// This contains the valid opcode combinations available
// in cmd/internal/obj/ppc64/asm9.go which exist for
// POWER10/ISA 3.1.

#include "../../../../../runtime/textflag.h"

TEXT asmtest(SB), DUPOK|NOSPLIT, $0
	BRD R1, R2                              // 7c220176

pkg debug/elf, const R_PPC64_ADDR32 R_PPC64
pkg debug/elf, const R_PPC64_ADDR64 = 38
pkg debug/elf, const R_PPC64_ADDR64 R_PPC64
pkg debug/elf, const R_PPC64_DTPMOD64 = 68
pkg debug/elf, const R_PPC64_DTPMOD64 R_PPC64
pkg debug/elf, const R_PPC64_DTPREL16 = 74
pkg debug/elf, const R_PPC64_DTPREL16 R_PPC64
pkg debug/elf, const R_PPC64_DTPREL16_DS = 101
pkg debug/elf, const R_PPC64_DTPREL16_DS R_PPC64

pkg debug/elf, const R_PPC64_PLTGOT_LO_DS R_PPC64
pkg debug/elf, const R_PPC64_REL16DX_HA = 246
pkg debug/elf, const R_PPC64_REL16DX_HA R_PPC64
pkg debug/elf, const R_PPC64_REL24_NOTOC = 116
pkg debug/elf, const R_PPC64_REL24_NOTOC R_PPC64
pkg debug/elf, const R_PPC64_SECTOFF_DS = 61
pkg debug/elf, const R_PPC64_SECTOFF_DS R_PPC64
pkg debug/elf, const R_PPC64_SECTOFF_LO_DS = 61

		register[obj.Rconv(i)] = int16(i)
	}
	for i := ppc64.REG_CR0; i <= ppc64.REG_CR7; i++ {
		register[obj.Rconv(i)] = int16(i)
	}
	for i := ppc64.REG_MSR; i <= ppc64.REG_CR; i++ {
		register[obj.Rconv(i)] = int16(i)
	}
	for i := ppc64.REG_CR0LT; i <= ppc64.REG_CR7SO; i++ {
		register[obj.Rconv(i)] = int16(i)
	}
	register["CR"] = ppc64.REG_CR
	register["XER"] = ppc64.REG_XER

// license that can be found in the LICENSE file.

//go:build (ppc64 || ppc64le) && internal

package cgotest

import "testing"

// If gcc is used, and linking internally, __mulsc3 and __muldc3
// will be linked in from libgcc which make several R_PPC64_TOC16_DS
// relocations which may not be resolvable with the internal linker.
func test8694(t *testing.T) { t.Skip("not supported on ppc64/ppc64le with internal linking") }

		} else {
			p.branch(targetAddr, targetProg)
		}
	case target.Type == obj.TYPE_MEM && target.Name == obj.NAME_NONE:
		// JMP 4(R0)
		*targetAddr = *target
		// On the ppc64, 9a encodes BR (CTR) as BR CTR. We do the same.
		if p.arch.Family == sys.PPC64 && target.Offset == 0 {
			targetAddr.Type = obj.TYPE_REG
		}
	case target.Type == obj.TYPE_CONST:
		// JMP $4
		*targetAddr = a[0]
	case target.Type == obj.TYPE_NONE:

pkg debug/elf, const R_PPC64_D34_LO = 129 #54345
pkg debug/elf, const R_PPC64_D34_LO R_PPC64 #54345
pkg debug/elf, const R_PPC64_D34 R_PPC64 #54345
pkg debug/elf, const R_PPC64_DTPREL34 = 147 #54345
pkg debug/elf, const R_PPC64_DTPREL34 R_PPC64 #54345
pkg debug/elf, const R_PPC64_GLOB_DAT = 20 #54345
pkg debug/elf, const R_PPC64_GLOB_DAT R_PPC64 #54345
pkg debug/elf, const R_PPC64_GNU_VTENTRY = 254 #54345

	for _, goppc64 := range []int{8, 9, 10} {
		t.Logf("GOPPC64=power%d", goppc64)
		buildcfg.GOPPC64 = goppc64
		// Some pseudo-ops may assemble differently depending on GOPPC64
		testEndToEnd(t, "ppc64", "ppc64")
		testEndToEnd(t, "ppc64", "ppc64_p10")
	}
}

func TestRISCVEndToEnd(t *testing.T) {
	testEndToEnd(t, "riscv64", "riscv64")
}

func TestRISCVErrors(t *testing.T) {
	testErrors(t, "riscv64", "riscv64error")