pass


def test_depends_hashable():
    dep()  # just for coverage
    d1 = Depends(dep)
    d2 = Depends(dep)
    d3 = Depends(dep, scope="function")
    d4 = Depends(dep, scope="function")

    s1 = Security(dep)
    s2 = Security(dep)

    assert hash(d1) == hash(d2)
    assert hash(s1) == hash(s2)
    assert hash(d1) != hash(d3)

        assertTrue(crawlingConfigHelper.getPipeline("W1").isEmpty());
        assertTrue(crawlingConfigHelper.getPipeline("F1").isEmpty());
        assertTrue(crawlingConfigHelper.getPipeline("D1").isEmpty());
        assertEquals("wp", crawlingConfigHelper.getPipeline("W1P").get());
        assertEquals("fp", crawlingConfigHelper.getPipeline("F1P").get());

	VREV64	V1.H4, V2.H8                                     // ERROR "invalid arrangement"
	VREV64	V1.D1, V2.D1                                     // ERROR "invalid arrangement"
	VREV16	V1.D1, V2.D1                                     // ERROR "invalid arrangement"
	VREV16	V1.B8, V2.B16                                    // ERROR "invalid arrangement"

	VLD1 (R24), [V18.D1, V19.D1, V20.D1]                        // 126f400c
	VLD1 (R29), [V14.D1, V15.D1, V16.D1, V17.D1]                // ae2f400c
	VLD1.P 16(R23), [V1.B16]                                    // e172df4c
	VLD1.P (R6)(R11), [V31.D1]                                  // df7ccb0c
	VLD1.P 16(R7), [V31.D1, V0.D1]                              // ffacdf0c

		curQ = 1
	case "H4":
		curSize = 1
		curQ = 0
	case "H8":
		curSize = 1
		curQ = 1
	case "S2":
		curSize = 2
		curQ = 0
	case "S4":
		curSize = 2
		curQ = 1
	case "D1":
		curSize = 3
		curQ = 0
	case "D2":
		curSize = 3
		curQ = 1
	default:
		return 0, errors.New("invalid arrangement in ARM64 register list")
	}

$round_consts<>(SB), R1 MOVD $24, R2 // counter for loop VLD1.P 16(R0), [V0.D1, V1.D1] VLD1.P 16(R0), [V2.D1, V3.D1] VLD1.P 16(R0), [V4.D1, V5.D1] VLD1.P 16(R0), [V6.D1, V7.D1] VLD1.P 16(R0), [V8.D1, V9.D1] VLD1.P 16(R0), [V10.D1, V11.D1] VLD1.P 16(R0), [V12.D1, V13.D1] VLD1.P 16(R0), [V14.D1, V15.D1] VLD1.P 16(R0), [V16.D1, V17.D1] VLD1.P 16(R0), [V18.D1, V19.D1] VLD1.P 16(R0), [V20.D1, V21.D1] VLD1.P 16(R0), [V22.D1, V23.D1] VLD1 (R0), [V24.D1] SUB $192, R0, R0 loop: // theta VEOR3 V20.B16, V15.B16, V10.B16,...

00000d0 3d f8 a7 60 24 61 c5 ef ae 9e c8 6c 6d 4e 69 c8
00000e0 67 65 34 f8 37 76 2d 76 5c 54 f3 95 65 49 c7 0f
00000f0 18 71 4b 7e 5b 6a d1 79 47 61 41 b0 4e 2a 74 45
0000100 43 58 12 b2 5a a5 c6 7d 68 55 88 d4 98 75 18 6d
0000110 08 d1 1f 8f 5a 9e 96 ee 45 cf a4 84 4e 4b e8 50
0000120 a7 13 d9 06 de 52 81 97 36 b2 d7 b8 fc 2b 5f 55
0000130 23 1f 32 59 cf 30 27 fb e2 8a b9 de 45 dd 63 9c

	SHA512SU0	V9.D2, V8.D2            // 2881c0ce
	SHA512SU1	V7.D2, V6.D2, V5.D2     // c58867ce
	VRAX1	V26.D2, V29.D2, V30.D2          // be8f7ace
	VXAR	$63, V27.D2, V21.D2, V26.D2     // bafe9bce
	VPMULL	V2.D1, V1.D1, V3.Q1             // 23e0e20e
	VPMULL2	V2.D2, V1.D2, V4.Q1             // 24e0e24e
	VPMULL	V2.B8, V1.B8, V3.H8             // 23e0220e
	VPMULL2	V2.B16, V1.B16, V4.H8           // 24e0224e