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Results 1 - 10 of 10 for FNEGD (0.06 sec)
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src/cmd/internal/obj/riscv/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 2.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 30.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64.s
SNEZ X15, X15 // b337f000 // F extension FABSS F0, F1 // d3200020 FNEGS F0, F1 // d3100020 FNES F0, F1, X7 // d3a300a093c31300 // D extension FABSD F0, F1 // d3200022 FNEGD F0, F1 // d3100022 FNED F0, F1, X5 // d3a200a293c21200 FLTD F0, F1, X5 // d39200a2 FLED F0, F1, X5 // d38200a2 FEQD F0, F1, X5 // d3a200a2
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 22 04:42:21 UTC 2024 - 16.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/RISCV64.rules
(F(MADD|NMADD|MSUB|NMSUB)S x y neg:(FNEGS z)) && neg.Uses == 1 => (F(MSUB|NMSUB|MADD|NMADD)S x y z) (F(MADD|NMADD|MSUB|NMSUB)D neg:(FNEGD x) y z) && neg.Uses == 1 => (F(NMSUB|MSUB|NMADD|MADD)D x y z)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 40.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteRISCV64.go
return true } break } return false } func rewriteValueRISCV64_OpRISCV64FMADDD(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMADDD neg:(FNEGD x) y z) // cond: neg.Uses == 1 // result: (FNMSUBD x y z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { neg := v_0 if neg.Op != OpRISCV64FNEGD { continue }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 205.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64Ops.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 58.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64.rules
// FP simplification (FNEGS (FMULS x y)) => (FNMULS x y) (FNEGD (FMULD x y)) => (FNMULD x y) (FMULS (FNEGS x) y) => (FNMULS x y) (FMULD (FNEGD x) y) => (FNMULD x y) (FNEGS (FNMULS x y)) => (FMULS x y) (FNEGD (FNMULD x y)) => (FMULD x y) (FNMULS (FNEGS x) y) => (FMULS x y) (FNMULD (FNEGD x) y) => (FMULD x y) (FADDS a (FMULS x y)) && a.Block.Func.useFMA(v) => (FMADDS a x y)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 113.1K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/obj.go
ins.as = AFSGNJXD ins.rs1 = uint32(p.From.Reg) case AFNEGS: // FNEGS rs, rd -> FSGNJNS rs, rs, rd ins.as = AFSGNJNS ins.rs1 = uint32(p.From.Reg) case AFNEGD: // FNEGD rs, rd -> FSGNJND rs, rs, rd ins.as = AFSGNJND ins.rs1 = uint32(p.From.Reg) case AROL, AROLW, AROR, ARORW: inss = instructionsForRotate(p, ins) case ARORI:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sun Apr 07 03:32:27 UTC 2024 - 77K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteARM64.go
} func rewriteValueARM64_OpARM64FNEGD(v *Value) bool { v_0 := v.Args[0] // match: (FNEGD (FMULD x y)) // result: (FNMULD x y) for { if v_0.Op != OpARM64FMULD { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64FNMULD) v.AddArg2(x, y) return true } // match: (FNEGD (FNMULD x y)) // result: (FMULD x y) for { if v_0.Op != OpARM64FNMULD { break
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 608.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNEGD", argLen: 1, asm: arm64.AFNEGD, reg: regInfo{ inputs: []inputInfo{
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)