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Results 1 - 10 of 33 for vsrad (0.06 sec)
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src/cmd/internal/obj/ppc64/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 6.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64.s
VSRW V1, V2, V3 // 10611284 VSRD V1, V2, V3 // 106116c4 VSR V1, V2, V3 // 106112c4 VSRO V1, V2, V3 // 1061144c VSLD V1, V2, V3 // 106115c4 VSRAB V1, V2, V3 // 10611304 VSRAH V1, V2, V3 // 10611344 VSRAW V1, V2, V3 // 10611384 VSRAD V1, V2, V3 // 106113c4
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 21:53:50 UTC 2024 - 50.2K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 22 17:16:14 UTC 2022 - 334.7K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/asm9.go
case AVSRD: return OPVX(4, 1732, 0, 0) /* vsrd - v2.07 */ case AVSRAB: return OPVX(4, 772, 0, 0) /* vsrab - v2.03 */ case AVSRAH: return OPVX(4, 836, 0, 0) /* vsrah - v2.03 */ case AVSRAW: return OPVX(4, 900, 0, 0) /* vsraw - v2.03 */ case AVSRAD: return OPVX(4, 964, 0, 0) /* vsrad - v2.07 */ case AVBPERMQ:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 13:55:28 UTC 2024 - 156.1K bytes - Viewed (0) -
src/cmd/internal/obj/s390x/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Sep 05 16:41:03 UTC 2023 - 7.1K bytes - Viewed (0) -
src/math/atanh_s390x.s
TEXT ·atanhAsm(SB), NOSPLIT, $0-16 FMOVD x+0(FP), F0 MOVD $·atanhrodataL10<>+0(SB), R5 LGDR F0, R1 WORD $0xC0393FEF //iilf %r3,1072693247 BYTE $0xFF BYTE $0xFF SRAD $32, R1 WORD $0xB9170021 //llgtr %r2,%r1 MOVW R2, R6 MOVW R3, R7 CMPBGT R6, R7, L2 WORD $0xC0392FFF //iilf %r3,805306367 BYTE $0xFF BYTE $0xFF MOVW R2, R6 MOVW R3, R7
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 23 20:52:57 UTC 2023 - 5.1K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/a.out.go
ARLDCL ARLDCLCC ARLDICL ARLDICLCC ARLDIC ARLDICCC ACLRLSLDI AROTL AROTLW ASLBIA ASLBIE ASLBMFEE ASLBMFEV ASLBMTE ASLD ASLDCC ASRD ASRAD ASRADCC ASRDCC AEXTSWSLI AEXTSWSLICC ASTDCCC ATD ASETB /* 64-bit pseudo operation */ ADWORD AREMD AREMDU /* more 64-bit operations */ AHRFID APOPCNTD
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 16K bytes - Viewed (0) -
test/codegen/arithmetic.go
// arm64:"TST\t[$]63",-"UDIV",-"ASR",-"AND" // ppc64x:"ANDCC",-"RLDICL",-"SRAD",-"CMP" a := n1%64 == 0 // signed divisible // 386:"TESTL\t[$]63",-"DIVL",-"SHRL" // amd64:"TESTQ\t[$]63",-"DIVQ",-"SHRQ" // arm:"AND\t[$]63",-".*udiv",-"SRA" // arm64:"TST\t[$]63",-"UDIV",-"ASR",-"AND" // ppc64x:"ANDCC",-"RLDICL",-"SRAD",-"CMP" b := n2%64 != 0 // signed indivisible return a, b }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 15:28:00 UTC 2024 - 15.2K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go
return true case OR, ORCC, ORC, ORCCC, AND, ANDCC, ANDC, ANDCCC, XOR, XORCC, NAND, NANDCC, EQV, EQVCC, NOR, NORCC: return true case SLW, SLWCC, SLD, SLDCC, SRW, SRAW, SRWCC, SRAWCC, SRD, SRDCC, SRAD, SRADCC: return true } return false } // revCondMap maps a conditional register bit to its inverse, if possible. var revCondMap = map[string]string{ "LT": "GE", "GT": "LE", "EQ": "NE", }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 22 17:16:14 UTC 2022 - 10.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64.rules
(Rsh8Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRD (MOVBZreg x) y) (Rsh64x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAD x y) (Rsh32x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAW x y) (Rsh16x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAD (MOVHreg x) y) (Rsh8x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAD (MOVBreg x) y) // Unbounded shifts. Go shifts saturate to 0 or -1 when shifting beyond the number of
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0)