CFLD	32(X10), X11				// ERROR "expected float prime register in rd position"
	CFLD	32(X5), F11				// ERROR "expected integer prime register in rs1 position"
	CFLD	-1(X10), F11				// ERROR "must be in range [0, 255]"
	CFLD	34(X10), F11				// ERROR "must be a multiple of 8"
	CFLD	256(X10), F11				// ERROR "must be in range [0, 255]"
	CSW	F11, 20(X10)				// ERROR "expected integer prime register in rs2 position"

	register["FS7"] = riscv.REG_FS7
	register["FS8"] = riscv.REG_FS8
	register["FS9"] = riscv.REG_FS9
	register["FS10"] = riscv.REG_FS10
	register["FS11"] = riscv.REG_FS11
	register["FT8"] = riscv.REG_FT8
	register["FT9"] = riscv.REG_FT9
	register["FT10"] = riscv.REG_FT10
	register["FT11"] = riscv.REG_FT11

	// Pseudo-registers.
	register["SB"] = RSB
	register["FP"] = RFP
	register["PC"] = RPC

	//TODO VFADDP V30.S4, V3.S4, V11.S4        // 6bd43e6e
	FCCMPS LE, F17, F12, $14                   // 8ed5311e
	FCCMPD HI, F11, F15, $15                   // ef856b1e
	FCCMPES HS, F28, F13, $13                  // bd253c1e
	FCCMPED LT, F20, F4, $9                    // 99b4741e
	//TODO FCMEQ F7, F11, F26                  // 7ae5675e
	//TODO VFCMEQ V29.S4, V26.S4, V30.S4       // 5ee73d4e

    <glob pattern="*.fh7"/>
    <glob pattern="*.fh8"/>
    <glob pattern="*.fh9"/>
    <glob pattern="*.fh10"/>
    <glob pattern="*.fh11"/>
    <glob pattern="*.fh12"/>
    <glob pattern="*.ft7"/>
    <glob pattern="*.ft8"/>
    <glob pattern="*.ft9"/>
    <glob pattern="*.ft10"/>
    <glob pattern="*.ft11"/>
    <glob pattern="*.ft12"/>
  </mime-type>

  <mime-type type="image/x-jbig2">

	CLFEBR	F15, R1                // b39c501f
	CLFDBR	F14, R2                // b39d502e
	CLGEBR	F13, R3                // b3ac503d
	CLGDBR	F12, R4                // b3ad504c

	FMOVS	$0, F11                // b37400b0
	FMOVD	$0, F12                // b37500c0
	FMOVS	(R1)(R2*1), F0         // 78021000
	FMOVS	n-8(SP), F15           // 78f0f010
	FMOVD	-9999999(R8)(R9*1), F8 // c0a1ff67698141aa9000688a8000

	FMADDF	F2, F14, F9, F16	// 30391108
	FMADDD	F11, F20, F23, F12	// ecd22508
	FMSUBF	F3, F11, F31, F22	// f6af5108
	FMSUBD	F13, F30, F9, F15	// 2ff96608
	FNMADDF	F27, F11, F5, F21	// b5ac9d08
	FNMADDD	F29, F14, F27, F6	// 66bbae08
	FNMSUBF	F17, F8, F12, F8	// 88a1d808
	FNMSUBD	F29, F21, F3, F17	// 71d4ee08
	FMADDF	F2, F14, F9		// 29391108
	FMADDD	F11, F20, F23		// f7d22508
	FMSUBF	F3, F11, F31		// ffaf5108

	{"F0", "F0"},
	{"F1", "F1"},
	{"F2", "F2"},
	{"F3", "F3"},
	{"F4", "F4"},
	{"F5", "F5"},
	{"F6", "F6"},
	{"F7", "F7"},
	{"F8", "F8"},
	{"F9", "F9"},
	{"F10", "F10"},
	{"F11", "F11"},
	{"F12", "F12"},
	{"F13", "F13"},
	{"F14", "F14"},
	{"F15", "F15"},
	{"V0", "V0"},
	{"V1", "V1"},
	{"V2", "V2"},
	{"V3", "V3"},
	{"V4", "V4"},
	{"V5", "V5"},
	{"V6", "V6"},

	FMOVD	F1, 1(R2) // 411000fc
	FMOVD	F1, 8(R2) // 410400fd
	FMOVD	F20, (R2) // 540000fd
	FMOVQ	F0, 32(R5)// a008803d
	FMOVQ	F10, 65520(R10) // 4afdbf3d
	FMOVQ	F11, 64(RSP)    // eb13803d
	FMOVQ	F11, 8(R20)     // 8b82803c
	FMOVQ	F11, 4(R20)     // 8b42803c

	MOVB	1(R1), R2 // 22048039
	MOVH	1(R1), R2 // 22108078
	MOVH	2(R1), R2 // 22048079
	MOVW	1(R1), R2 // 221080b8
	MOVW	4(R1), R2 // 220480b9

	CFSDSP	F10, 32(SP)				// 2ab0

	// 26.3.2: Compressed Register-Based Loads and Stores
	CLW	20(X10), X11				// 4c49
	CLD	24(X10), X11				// 0c6d
	CFLD	32(X10), F11				// 0c31
	CSW	X11, 20(X10)				// 4cc9
	CSD	X11, 24(X10)				// 0ced
	CFSD	F11, 32(X10)				// 0cb1

	// 26.4: Compressed Control Transfer Instructions
	CJ	1(PC)					// 09a0
	CJR	X5					// 8282
	CJALR	X5					// 8292
	CBEQZ	X10, 1(PC)				// 09c1

F90F          ; mapped                 ; 7F85          # 1.1  CJK COMPATIBILITY IDEOGRAPH-F90F
F910          ; mapped                 ; 863F          # 1.1  CJK COMPATIBILITY IDEOGRAPH-F910
F911          ; mapped                 ; 87BA          # 1.1  CJK COMPATIBILITY IDEOGRAPH-F911
F912          ; mapped                 ; 88F8          # 1.1  CJK COMPATIBILITY IDEOGRAPH-F912
F913          ; mapped                 ; 908F          # 1.1  CJK COMPATIBILITY IDEOGRAPH-F913