SBC	R0->28, R1           // 401ec1e0
	SBC	R0@>28, R1           // 601ec1e0
	SBC.S	R0<<28, R1           // 001ed1e0
	SBC.S	R0>>28, R1           // 201ed1e0
	SBC.S	R0->28, R1           // 401ed1e0
	SBC.S	R0@>28, R1           // 601ed1e0
	SBC	R0<<R1, R2, R3       // 1031c2e0
	SBC	R0>>R1, R2, R3       // 3031c2e0
	SBC	R0->R1, R2, R3       // 5031c2e0
	SBC	R0@>R1, R2, R3       // 7031c2e0

	DMB	MB_ISH
	MOVW	time_hi2(R3), R2
	CMP	R1, R2
	BNE	wall

	// w = R1:R0 in 100ns untis
	// convert to Unix epoch (but still 100ns units)
	#define delta 116444736000000000
	SUB.S   $(delta & 0xFFFFFFFF), R0
	SBC     $(delta >> 32), R1

	// Convert to nSec
	MOVW    $100, R2
	MULLU   R0, R2, (R4, R3)    // R4:R3 = R1:R0 * R2
	MULA    R1, R2, R4, R4
	// w = R2:R1 in nSec
	MOVW    R3, R1	      // R4:R3 -> R2:R1
	MOVW    R4, R2

	RET


// func subVV(z, x, y []Word) (c Word)
// (same as addVV except for SBC instead of ADC and label names)
TEXT ·subVV(SB),NOSPLIT,$0
	SUB.S	$0, R0		// clear borrow flag
	MOVW	z+0(FP), R1
	MOVW	z_len+4(FP), R4
	MOVW	x+12(FP), R2
	MOVW	y+24(FP), R3
	ADD	R4<<2, R1, R4
	B E2
L2:
	MOVW.P	4(R2), R5
	MOVW.P	4(R3), R6
	SBC.S	R6, R5
	MOVW.P	R5, 4(R1)
E2:
	TEQ	R1, R4
	BNE L2

	MOVW	$0, R0

	"ORN",
	"ORNW",
	"ORR",
	"ORRW",
	"PRFM",
	"PRFUM",
	"RBIT",
	"RBITW",
	"REM",
	"REMW",
	"REV",
	"REV16",
	"REV16W",
	"REV32",
	"REVW",
	"ROR",
	"RORW",
	"SBC",
	"SBCS",
	"SBCSW",
	"SBCW",
	"SBFIZ",
	"SBFIZW",
	"SBFM",
	"SBFMW",
	"SBFX",
	"SBFXW",
	"SCVTFD",
	"SCVTFS",
	"SCVTFWD",
	"SCVTFWS",
	"SDIV",
	"SDIVW",
	"SEV",

		{name: "RSBSconst", argLength: 1, reg: gp11carry, asm: "RSB", aux: "Int32"}, // auxInt - arg0, set carry flag
		{name: "SBC", argLength: 3, reg: gp2flags1, asm: "SBC"},                     // arg0 - arg1 - carry, arg2=flags
		{name: "SBCconst", argLength: 2, reg: gp1flags1, asm: "SBC", aux: "Int32"},  // arg0 - auxInt - carry, arg1=flags

(SUB (SRA y z) x) => (RSBshiftRAreg x y z)
(SBC x (SLLconst [c] y) flags) => (SBCshiftLL x y [c] flags)
(SBC (SLLconst [c] y) x flags) => (RSCshiftLL x y [c] flags)
(SBC x (SRLconst [c] y) flags) => (SBCshiftRL x y [c] flags)
(SBC (SRLconst [c] y) x flags) => (RSCshiftRL x y [c] flags)
(SBC x (SRAconst [c] y) flags) => (SBCshiftRA x y [c] flags)
(SBC (SRAconst [c] y) x flags) => (RSCshiftRA x y [c] flags)
(SBC x (SLL y z) flags) => (SBCshiftLLreg x y z flags)

	MOVD	$0, acc2
	MOVD	p256const1<>(SB), acc3
	// Load the original value
	LDP	0*16(a_ptr), (t0, t1)
	LDP	1*16(a_ptr), (t2, t3)
	// Speculatively subtract
	SUBS	t0, acc0
	SBCS	t1, acc1
	SBCS	t2, acc2
	SBC	t3, acc3
	// If condition is 0, keep original value
	CMP	$0, hlp0
	CSEL	EQ, t0, acc0, acc0
	CSEL	EQ, t1, acc1, acc1
	CSEL	EQ, t2, acc2, acc2
	CSEL	EQ, t3, acc3, acc3
	// Store result

			as2 = p.As // ADD, SUB, ORR, EOR, BIC
		case ARSB:
			as2 = AADD // RSB -> RSB/ADD pair
		case AADC:
			as2 = AADD // ADC -> ADC/ADD pair
		case ASBC:
			as2 = ASUB // SBC -> SBC/SUB pair
		case ARSC:
			as2 = AADD // RSC -> RSC/ADD pair
		default:
			c.ctxt.Diag("unknown second op for %v", p)
		}
		o1 = c.oprrr(p, p.As, int(p.Scond))
		o2 = c.oprrr(p, as2, int(p.Scond))

	RORW $28, R14, R15                         // cf718e13
	RORW R3, R12, R3                           // 832dc31a
	ROR R0, R23, R2                            // e22ec09a
	SBCW R4, R8, R24                           // 1801045a
	SBC R25, R10, R26                          // 5a0119da
	SBCSW R27, R19, R19                        // 73021b7a
	SBCS R5, R9, R5                            // 250105fa
	SBFIZW $9, R10, $18, R22                   // 56451713

	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SBC (MOVWconst [c]) x flags)
	// result: (RSCconst [c] x flags)
	for {
		if v_0.Op != OpARMMOVWconst {
			break
		}
		c := auxIntToInt32(v_0.AuxInt)
		x := v_1
		flags := v_2
		v.reset(OpARMRSCconst)
		v.AuxInt = int32ToAuxInt(c)
		v.AddArg2(x, flags)
		return true
	}
	// match: (SBC x (MOVWconst [c]) flags)