CLREX $0                                   // 5f3003d5
	CLSW R15, R6                               // e615c05a
	CLS R15, ZR                                // ff15c0da
	CLZW R1, R14                               // 2e10c05a
	CLZ R21, R9                                // a912c0da
	CMNW R21.UXTB<<4, R15                      // ff11352b
	CMN R0.UXTW<<4, R16                        // 1f5220ab

	VLD1R.P	(R15)(R1), [V15.H4]                             // efc5c10d
	VLD2R	(R15), [V15.H4, V16.H4]                         // efc5600d
	VLD2R.P	16(R0), [V0.D2, V1.D2]                          // 00ccff4d
	VLD2R.P	(R0)(R5), [V31.D1, V0.D1]                       // 1fcce50d
	VLD3R	(RSP), [V31.S2, V0.S2, V1.S2]                   // ffeb400d
	VLD3R.P	6(R15), [V15.H4, V16.H4, V17.H4]                // efe5df0d

	}
	if name[0] != 'R' {
		p.errorf("expected g or R0 through R15; found %s", name)
		return 0
	}
	r, ok := p.registerReference(name)
	if !ok {
		return 0
	}
	reg := r - p.arch.Register["R0"]
	if reg < 0 {
		// Could happen for an architecture having other registers prefixed by R
		p.errorf("expected g or R0 through R15; found %s", name)
		return 0
	}
	return uint16(reg)
}

	MRS	PMSWINC_EL0, R3                                  // ERROR "system register is not readable"
	MRS	OSLAR_EL1, R3                                    // ERROR "system register is not readable"
	VLD3R.P	24(R15), [V15.H4,V16.H4,V17.H4]                  // ERROR "invalid post-increment offset"
	VBIT	V1.H4, V12.H4, V3.H4                             // ERROR "invalid arrangement"