func bitcheck64_constleft(a uint64) (n int) {
	// amd64:"BTQ\t[$]63"
	if a&(1<<63) != 0 {
		return 1
	}
	// amd64:"BTQ\t[$]60"
	if a&(1<<60) != 0 {
		return 1
	}
	// amd64:"BTL\t[$]0"
	if a&(1<<0) != 0 {
		return 1
	}
	return 0
}

func bitcheck64_constright(a [8]uint64) (n int) {
	// amd64:"BTQ\t[$]63"
	if (a[0]>>63)&1 != 0 {
		return 1
	}
	// amd64:"BTQ\t[$]63"
	if a[1]>>63 != 0 {
		return 1
	}

	"BLSMSKQ",
	"BLSRL",
	"BLSRQ",
	"BOUNDL",
	"BOUNDW",
	"BSFL",
	"BSFQ",
	"BSFW",
	"BSRL",
	"BSRQ",
	"BSRW",
	"BSWAPL",
	"BSWAPQ",
	"BTCL",
	"BTCQ",
	"BTCW",
	"BTL",
	"BTQ",
	"BTRL",
	"BTRQ",
	"BTRW",
	"BTSL",
	"BTSQ",
	"BTSW",
	"BTW",
	"BYTE",
	"BZHIL",
	"BZHIQ",
	"CBW",
	"CDQ",
	"CDQE",
	"CLAC",
	"CLC",
	"CLD",
	"CLDEMOTE",
	"CLFLUSH",

// mutandis, for UGE and SETAE, and CC and SETCC.
((NE|EQ) (TESTL (SHLL (MOVLconst [1]) x) y)) => ((ULT|UGE) (BTL x y))
((NE|EQ) (TESTQ (SHLQ (MOVQconst [1]) x) y)) => ((ULT|UGE) (BTQ x y))
((NE|EQ) (TESTLconst [c] x)) && isUint32PowerOfTwo(int64(c))
    => ((ULT|UGE) (BTLconst [int8(log32(c))] x))
((NE|EQ) (TESTQconst [c] x)) && isUint64PowerOfTwo(int64(c))
    => ((ULT|UGE) (BTQconst [int8(log32(c))] x))

		// bit test/set/clear operations
		{name: "BTL", argLength: 2, reg: gp2flags, asm: "BTL", typ: "Flags"},                                           // test whether bit arg0%32 in arg1 is set
		{name: "BTQ", argLength: 2, reg: gp2flags, asm: "BTQ", typ: "Flags"},                                           // test whether bit arg0%64 in arg1 is set

		if !(c > d) {
			break
		}
		v.reset(OpAMD64BTLconst)
		v.AuxInt = int8ToAuxInt(c - d)
		v.AddArg(x)
		return true
	}
	// match: (BTLconst [0] s:(SHRQ x y))
	// result: (BTQ y x)
	for {
		if auxIntToInt8(v.AuxInt) != 0 {
			break
		}
		s := v_0
		if s.Op != OpAMD64SHRQ {
			break
		}
		y := s.Args[1]
		x := s.Args[0]
		v.reset(OpAMD64BTQ)

			inputs: []inputInfo{
				{0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:   "BTQ",
		argLen: 2,
		asm:    x86.ABTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15