val b1: Int
      get() =
        when {
          codepointDelta < 0 -> 0x40 or (absoluteDelta shr 14)
          codepointDelta > 0 -> 0x50 or (absoluteDelta shr 14)
          else -> error("Unexpected codepointDelta of 0")
        }

    val b2: Int
      get() = absoluteDelta shr 7 and 0x7f

    val b3: Int
      get() = absoluteDelta and 0x7f

    companion object {

    val sectionOffset = rangesBuffer.size.toInt() / 4

    // Section prefix.
    sectionIndexBuffer.writeByte(section and 0x1fc000 shr 14)
    sectionIndexBuffer.writeByte((section and 0x3f80) shr 7)

    // Section index.
    sectionIndexBuffer.writeByte((sectionOffset and 0x3f80) shr 7)
    sectionIndexBuffer.writeByte(sectionOffset and 0x7f)

    // Ranges.
    for (range in sectionMappedRanges) {

      val lengthByteCount = (lengthBitCount + 7) / 8
      sink.writeByte(0b1000_0000 or lengthByteCount)
      for (shift in (lengthByteCount - 1) * 8 downTo 0 step 8) {
        sink.writeByte((length shr shift).toInt())
      }
    }

    // Write the payload.
    sink.writeAll(content)
  }

  /**
   * Execute [block] with a new namespace for type hints. Type hints from the enclosing type are no

	STRING // "abc"
	literal_end

	operator_beg
	// Operators and delimiters
	ADD // +
	SUB // -
	MUL // *
	QUO // /
	REM // %

	AND     // &
	OR      // |
	XOR     // ^
	SHL     // <<
	SHR     // >>
	AND_NOT // &^

	ADD_ASSIGN // +=
	SUB_ASSIGN // -=
	MUL_ASSIGN // *=
	QUO_ASSIGN // /=
	REM_ASSIGN // %=

	AND_ASSIGN     // &=
	OR_ASSIGN      // |=
	XOR_ASSIGN     // ^=

	switch {
	case n == 0:
		return u1, u2
	case n == 64:
		return 0, u1 | nonzero(u2)
	case n >= 128:
		return 0, nonzero(u1 | u2)
	case n < 64:
		r1, r2 = shr(u1, u2, n)
		r2 |= nonzero(u2 & (1<<n - 1))
	case n < 128:
		r1, r2 = shr(u1, u2, n)
		r2 |= nonzero(u1&(1<<(n-64)-1) | u2)
	}
	return
}

func lz(u1, u2 uint64) (l int32) {
	l = int32(bits.LeadingZeros64(u1))
	if l == 64 {

(MOVBQZX x) && zeroUpper56Bits(x,3)...

	MOVL	(index*4)(SI), AX; \
	BSWAPL	AX; \
	MOVL	AX, (index*4)(BP)

// Wt = SIGMA1(Wt-2) + Wt-7 + SIGMA0(Wt-15) + Wt-16; for 16 <= t <= 63
//   SIGMA0(x) = ROTR(7,x) XOR ROTR(18,x) XOR SHR(3,x)
//   SIGMA1(x) = ROTR(17,x) XOR ROTR(19,x) XOR SHR(10,x)
#define MSGSCHEDULE1(index) \
	MOVL	((index-2)*4)(BP), AX; \
	MOVL	AX, CX; \
	RORL	$17, AX; \
	MOVL	CX, DX; \
	RORL	$19, CX; \
	SHRL	$10, DX; \
	MOVL	((index-15)*4)(BP), BX; \

	// amd64:"SHRQ.*,.*,"
	shr := x>>s | y<<ŝ
	// amd64:"SHLQ.*,.*,"
	shl := x<<s | y>>ŝ
	return shr, shl
}

func checkShiftToMask(u []uint64, s []int64) {
	// amd64:-"SHR",-"SHL","ANDQ"
	u[0] = u[0] >> 5 << 5
	// amd64:-"SAR",-"SHL","ANDQ"
	s[0] = s[0] >> 5 << 5
	// amd64:-"SHR",-"SHL","ANDQ"
	u[1] = u[1] << 5 >> 5

      accumulator = (accumulator shl codeBitCount) or code.toLong()
      accumulatorBitCount += codeBitCount

      while (accumulatorBitCount >= 8) {
        accumulatorBitCount -= 8
        sink.writeByte((accumulator shr accumulatorBitCount).toInt())
      }
    }

    if (accumulatorBitCount > 0) {
      accumulator = accumulator shl (8 - accumulatorBitCount)
      accumulator = accumulator or (0xffL ushr accumulatorBitCount)

	Gtr // >
	Geq // >=

	// precAdd
	Add // +
	Sub // -
	Or  // |
	Xor // ^

	// precMul
	Mul    // *
	Div    // /
	Rem    // %
	And    // &
	AndNot // &^
	Shl    // <<
	Shr    // >>
)

// Operator precedences
const (
	_ = iota
	precOrOr
	precAndAnd
	precCmp
	precAdd
	precMul