MOVHU.P	-0x24(R9), R8        // MOVHU.P -36(R9), R8       // b48259e0
	MOVH	-0x24(R9), R8        // MOVH -36(R9), R8          // f48259e1
	MOVH.W	-0x24(R9), R8        // MOVH.W -36(R9), R8        // f48279e1
	MOVH.P	-0x24(R9), R8        // MOVH.P -36(R9), R8        // f48259e0
	MOVHS	-0x24(R9), R8        // MOVHS -36(R9), R8         // f48259e1

	RISBLGZ	$9, $24, $11, R11, R0 // ec0b09980b51

	LAA	R1, R2, 524287(R3)    // eb213fff7ff8
	LAAG	R4, R5, -524288(R6)   // eb54600080e8
	LAAL	R7, R8, 8192(R9)      // eb87900002fa
	LAALG	R10, R11, -8192(R12)  // ebbac000feea
	LAN	R1, R2, (R3)          // eb21300000f4
	LANG	R4, R5, (R6)          // eb54600000e4
	LAX	R7, R8, (R9)          // eb87900000f7
	LAXG	R10, R11, (R12)       // ebbac00000e7

	MOVFD	F0, F1        // c01ab7ee
	MOVDF	F4, F5        // c45bb7ee

	LDREX	(R8), R9      // 9f9f98e1
	LDREXB	(R11), R12    // 9fcfdbe1
	LDREXD	(R11), R12    // 9fcfbbe1
	STREX	R3, (R4), R5  // STREX  (R4), R3, R5 // 935f84e1
	STREXB	R8, (R9), g   // STREXB (R9), R8, g  // 98afc9e1
	STREXD	R8, (R9), g   // STREXD (R9), R8, g  // 98afa9e1

	CMPF    F8, F9        // c89ab4ee10faf1ee
	CMPD.CS F4, F5        // c45bb42e10faf12e

	CASALW	R5, (RSP), R7                        // e7ffe588
	CASALH	ZR, (R5), R8                         // a8fcff48
	CASALB	R8, (R9), ZR                         // 3ffde808
	CASPD	(R30, ZR), (RSP), (R8, R9)           // e87f3e48
	CASPW	(R6, R7), (R8), (R4, R5)             // 047d2608
	CASPD	(R2, R3), (R2), (R8, R9)             // 487c2248

// RET
	RET                                        // c0035fd6
	RET R0					   // 00005fd6

	MOVW.S	$124, R1           // ERROR "invalid .S suffix"
	MVN.S	$123, g            // ERROR "invalid .S suffix"
	RSB.U	$0, R9             // ERROR "invalid .U suffix"
	CMP.S	$29, g             // ERROR "invalid .S suffix"
	ADD.W	R1<<R2, R3         // ERROR "invalid .W suffix"
	SUB.U	R1<<R2, R3, R9     // ERROR "invalid .U suffix"
	CMN.S	R5->R2, R1         // ERROR "invalid .S suffix"
	SLL.P	R1, R2, R3         // ERROR "invalid .P suffix"

	VLD1.P	(R8)(R9.SXTX<<2), [V2.B16]                       // ERROR "invalid extended register"
	VLD1.P	(R8)(R9<<2), [V2.B16]                            // ERROR "invalid extended register"
	VST1.P	[V1.B16], (R8)(R9.UXTW)                          // ERROR "invalid extended register"
	VST1.P	[V1.B16], (R8)(R9<<1)                            // ERROR "invalid extended register"

The range of registers is specified by a start register and an end register.
For example, <code>LMG</code> <code>(R9),</code> <code>R5,</code> <code>R7</code> would load
<code>R5</code>, <code>R6</code> and <code>R7</code> with the 64-bit values at
<code>0(R9)</code>, <code>8(R9)</code> and <code>16(R9)</code> respectively.
</p>

<p>
Storage-and-storage instructions such as <code>MVC</code> and <code>XC</code> are written

func (p *Parser) branch(addr *obj.Addr, target *obj.Prog) {
	*addr = obj.Addr{
		Type:  obj.TYPE_BRANCH,
		Index: 0,
	}
	addr.Val = target
}

// asmInstruction assembles an instruction.
// MOVW R9, (R10)
func (p *Parser) asmInstruction(op obj.As, cond string, a []obj.Addr) {
	// fmt.Printf("%s %+v\n", op, a)
	prog := &obj.Prog{
		Ctxt: p.ctxt,
		Pos:  p.pos(),
		As:   op,
	}
	switch len(a) {