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Results 1 - 6 of 6 for pli (0.12 sec)
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staging/src/k8s.io/apiserver/pkg/util/flowcontrol/apf_controller.go
cfgCtlr.lockAndDigestConfigObjects(nil, nil) fci := config.InformerFactory.Flowcontrol().V1() pli := fci.PriorityLevelConfigurations() fsi := fci.FlowSchemas() cfgCtlr.plLister = pli.Lister() cfgCtlr.plInformerSynced = pli.Informer().HasSynced cfgCtlr.fsLister = fsi.Lister() cfgCtlr.fsInformerSynced = fsi.Informer().HasSynced pli.Informer().AddEventHandler(cache.ResourceEventHandlerFuncs{ AddFunc: func(obj interface{}) {
Registered: Sat Jun 15 01:39:40 UTC 2024 - Last Modified: Sat May 04 18:33:12 UTC 2024 - 48.8K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/arm/armasm/plan9x.go
default: panic(fmt.Sprintf("wrong FP register: %v", inst)) } } } } // Move addressing mode into opcode suffix. suffix := "" switch inst.Op &^ 15 { case PLD, PLI, PLD_W: if mem, ok := inst.Args[0].(Mem); ok { args[0], suffix = memOpTrans(mem) } else { panic(fmt.Sprintf("illegal instruction: %v", inst)) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:33 UTC 2023 - 11.9K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/gnu.go
// the only valid mnemonic for paddi (R=1), In this case, RA must // always be 0. Otherwise it is invalid. r := inst.Args[3].(Imm) ra := inst.Args[1].(Reg) str := opName if ra == R0 { name := []string{"pli", "pla"} str = fmt.Sprintf("%s %s,%s", name[r&1], gnuArg(&inst, 0, inst.Args[0], PC), gnuArg(&inst, 2, inst.Args[2], PC)) startArg = 4 } else { str = fmt.Sprintf("%s %s,%s,%s", opName,
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:33 UTC 2023 - 12.2K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/inst.go
prf_type := (i >> 3) & (1<<2 - 1) prf_target := (i >> 1) & (1<<2 - 1) prf_policy := i & 1 var result string switch prf_type { case 0: result = "PLD" case 1: result = "PLI" case 2: result = "PST" case 3: return fmt.Sprintf("#%#02x", uint8(i)) } switch prf_target { case 0: result += "L1" case 1: result += "L2" case 2: result += "L3"
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:33 UTC 2023 - 21.5K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64.s
// Hex constant 0xFFFFFFFF80000001 MOVD $-2147483647, R5 // 3ca0800060a50001 or 0603800038a00001 // Hex constant 0xFFFFFFFE00000002 (load of constant on < power10, pli on >= power10 MOVD $-8589934590, R5 // 3ca00000e8a50000 or 0602000038a00002 // For backwards compatibility, MOVW $const,Rx and MOVWZ $const,Rx assemble identically // and accept the same constants.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 21:53:50 UTC 2024 - 50.2K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/obj9.go
isS32 := int64(int32(p.From.Offset)) == p.From.Offset isU32 := uint64(uint32(p.From.Offset)) == uint64(p.From.Offset) // If prefixed instructions are supported, a 34b signed constant can be generated by one pli instruction. isS34 := pfxEnabled && (p.From.Offset<<30)>>30 == p.From.Offset // Try converting MOVD $const,Rx into ADDIS/ORIS $s32>>16,R0,Rx switch { case isS32 && p.From.Offset&0xFFFF == 0 && p.From.Offset != 0:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 18:17:17 UTC 2024 - 40.8K bytes - Viewed (0)