VSOXEI8V	V3, V2, (V1)			// ERROR "expected integer register in rs1 position"
	VSOXEI8V	V3, X11, V0, (X10)		// ERROR "expected vector register in vs2 position"
	VL1RV		(X10), X10			// ERROR "expected vector register in vd position"
	VL1RV		(V1), V3			// ERROR "expected integer register in rs1 position"
	VS1RV		X11, (X11)			// ERROR "expected vector register in vs1 position"

	VSUXEI8V	V3, V2, V1, (X10)		// ERROR "invalid vector mask register"
	VLOXEI8V	(X10), V2, V1, V3		// ERROR "invalid vector mask register"
	VSOXEI8V	V3, V2, V1, (X10)		// ERROR "invalid vector mask register"
	VL1RV		(X10), V0, V3			// ERROR "too many operands for instruction"
	VS1RV		V3, V0, (X11)			// ERROR "too many operands for instruction"
	VADDVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"

	VSOXEI32V	V3, V2, V0, (X10)		// a761250c
	VSOXEI64V	V3, V2, (X10)			// a771250e
	VSOXEI64V	V3, V2, V0, (X10)		// a771250c

	// 31.7.9: Vector Load/Store Whole Register Instructions
	VL1RV		(X10), V3			// 87018502
	VL1RE8V		(X10), V3			// 87018502
	VL1RE16V	(X10), V3			// 87518502
	VL1RE32V	(X10), V3			// 87618502
	VL1RE64V	(X10), V3			// 87718502
	VL2RV		(X10), V2			// 07018522