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  2. github.com/golang/go

    src/cmd/asm/internal/asm/testdata/riscv64validation.s 

    	VSUXSEG2EI8V	V3, X11, V0, (X10)		// ERROR "expected vector register in vs2 position"
	VLOXSEG2EI8V	(X10), V2, X11			// ERROR "expected vector register in vd position"
	VLOXSEG2EI8V	(V1), V2, V3			// ERROR "expected integer register in rs1 position"
	VLOXSEG2EI8V	(X10), X11, V0, V3		// ERROR "expected vector register in vs2 position"
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Thu Nov 13 12:17:37 GMT 2025
    - 42.1K bytes
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