MOVL R10, R11 XORL R12, R11 BSWAPL R11 MOVL R11, 172(SP) MOVOU X11, 176(SP) ADDL $0x01, R10 MOVL R10, R11 XORL R12, R11 BSWAPL R11 MOVL R11, 188(SP) MOVOU X11, 192(SP) ADDL $0x01, R10 MOVL R10, R11 XORL R12, R11 BSWAPL R11 MOVL R11, 204(SP) MOVOU X11, 208(SP) ADDL $0x01, R10 MOVL R10, R11 XORL R12, R11 BSWAPL R11 MOVL R11, 220(SP) MOVOU X11, 224(SP) ADDL $0x01, R10 MOVL R10, R11 XORL R12, R11 BSWAPL R11 MOVL R11, 236(SP) MOVOU X11, 240(SP) ADDL $0x01, R10 MOVL R10, R11 XORL R12, R11 BSWAPL R11 MOVL...

	STLXP	(R6, R3), (R10), R2                  // 468d22c8
	STLXPW	(R6, R11), (R22), R21                // c6ae3588
	STLXRW	R1, (R0), R3                         // 01fc0388
	STXP	(R1, R2), (R3), R10                  // 61082ac8
	STXP	(R1, R2), (RSP), R10                 // e10b2ac8
	STXPW	(R1, R2), (R3), R10                  // 61082a88
	STXPW	(R1, R2), (RSP), R10                 // e10b2a88

	VADDPD 8(R10), Z10, K4, Z10      // 6251ad4c589208000000
	VADDPD (R10)(AX*4), Z20, K7, Z20 // 62c1dd47582482
	// EVEX gather (also tests Z as VSIB index).
	VPGATHERDD 360(AX)(X2*4), K1, X1    // 62f27d09904c905a
	VPGATHERDD 640(BP)(X15*8), K3, X14  // 62327d0b90b4fd80020000
	VPGATHERDD 960(R10)(X25*2), K7, X24 // 62027d0790844ac0030000
	VPGATHERDD 1280(R10)(X1*4), K4, X0  // 62d27d0c90848a00050000

	RISBLGZ	$9, $24, $11, R11, R0 // ec0b09980b51

	LAA	R1, R2, 524287(R3)    // eb213fff7ff8
	LAAG	R4, R5, -524288(R6)   // eb54600080e8
	LAAL	R7, R8, 8192(R9)      // eb87900002fa
	LAALG	R10, R11, -8192(R12)  // ebbac000feea
	LAN	R1, R2, (R3)          // eb21300000f4
	LANG	R4, R5, (R6)          // eb54600000e4
	LAX	R7, R8, (R9)          // eb87900000f7
	LAXG	R10, R11, (R12)       // ebbac00000e7

	MOVD	(R3)(R7.SXTX<<2), R8                             // ERROR "invalid index shift amount"
	MOVWU	(R5)(R4.UXTW<<3), R10                            // ERROR "invalid index shift amount"
	MOVWU	(R5)(R4<<1), R10                                 // ERROR "invalid index shift amount"
	MOVB	(R5)(R4.SXTW<<5), R10                            // ERROR "invalid index shift amount"

	// Note that there is no list of names as there is for x86.
	for i := arm.REG_R0; i < arm.REG_SPSR; i++ {
		register[obj.Rconv(i)] = int16(i)
	}
	// Avoid unintentionally clobbering g using R10.
	delete(register, "R10")
	register["g"] = arm.REG_R10
	for i := 0; i < 16; i++ {
		register[fmt.Sprintf("C%d", i)] = int16(i)
	}

	// Pseudo-registers.
	register["SB"] = RSB
	register["FP"] = RFP

	p.expectOperandEnd()
	return
}

// atStartOfRegister reports whether the parser is at the start of a register definition.
func (p *Parser) atStartOfRegister(name string) bool {
	// Simple register: R10.
	_, present := p.arch.Register[name]
	if present {
		return true
	}
	// Parenthesized register: R(10).
	return p.arch.RegisterPrefix[name] && p.peek() == '('
}

func (p *Parser) branch(addr *obj.Addr, target *obj.Prog) {
	*addr = obj.Addr{
		Type:  obj.TYPE_BRANCH,
		Index: 0,
	}
	addr.Val = target
}

// asmInstruction assembles an instruction.
// MOVW R9, (R10)
func (p *Parser) asmInstruction(op obj.As, cond string, a []obj.Addr) {
	// fmt.Printf("%s %+v\n", op, a)
	prog := &obj.Prog{
		Ctxt: p.ctxt,
		Pos:  p.pos(),
		As:   op,
	}
	switch len(a) {
	case 0: