(Rsh32Ux32 x y) => (CMOVWHSconst (SRL <x.Type> x y) (CMPconst [256] y) [0])
(Rsh32Ux16 x y) => (CMOVWHSconst (SRL <x.Type> x (ZeroExt16to32 y)) (CMPconst [256] (ZeroExt16to32 y)) [0])
(Rsh32Ux8  x y) => (SRL x (ZeroExt8to32 y))

(Rsh16Ux32 x y) => (CMOVWHSconst (SRL <x.Type> (ZeroExt16to32 x) y) (CMPconst [256] y) [0])

	SRL.S	$31, R5, R6          // a56fb0e1
	SRL	$14, R5              // 2557a0e1
	SRL	$15, R5              // a557a0e1
	SRL	$30, R5              // 255fa0e1
	SRL	$31, R5              // a55fa0e1
	SRL.S	$14, R5              // 2557b0e1
	SRL.S	$15, R5              // a557b0e1
	SRL.S	$30, R5              // 255fb0e1
	SRL.S	$31, R5              // a55fb0e1
	SRL	R5, R6, R7           // 3675a0e1
	SRL.S	R5, R6, R7           // 3675b0e1

		// Rotation instructions are supported natively.
		return []*instruction{ins}
	}

	switch ins.as {
	case AROL, AROLW, AROR, ARORW:
		// ROL -> OR (SLL x y) (SRL x (NEG y))
		// ROR -> OR (SRL x y) (SLL x (NEG y))
		sllOp, srlOp := ASLL, ASRL
		if ins.as == AROLW || ins.as == ARORW {
			sllOp, srlOp = ASLLW, ASRLW
		}
		shift1, shift2 := sllOp, srlOp

		{name: "SLLconst", argLength: 1, reg: gp11, asm: "LSL", aux: "Int64"},     // arg0 << auxInt, auxInt should be in the range 0 to 63.
		{name: "SRL", argLength: 2, reg: gp21, asm: "LSR"},                        // arg0 >> arg1, unsigned, shift amount is mod 64