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Results 1 - 7 of 7 for SLL (0.03 sec)
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src/cmd/compile/internal/ssa/_gen/ARM.rules
(Lsh32x32 x y) => (CMOVWHSconst (SLL <x.Type> x y) (CMPconst [256] y) [0]) (Lsh32x16 x y) => (CMOVWHSconst (SLL <x.Type> x (ZeroExt16to32 y)) (CMPconst [256] (ZeroExt16to32 y)) [0]) (Lsh32x8 x y) => (SLL x (ZeroExt8to32 y)) (Lsh16x32 x y) => (CMOVWHSconst (SLL <x.Type> x y) (CMPconst [256] y) [0]) (Lsh16x16 x y) => (CMOVWHSconst (SLL <x.Type> x (ZeroExt16to32 y)) (CMPconst [256] (ZeroExt16to32 y)) [0])
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 20 17:19:36 UTC 2023 - 90.1K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm.s
SLL $14, R5 // 0557a0e1 SLL $15, R5 // 8557a0e1 SLL $30, R5 // 055fa0e1 SLL $31, R5 // 855fa0e1 SLL.S $14, R5 // 0557b0e1 SLL.S $15, R5 // 8557b0e1 SLL.S $30, R5 // 055fb0e1 SLL.S $31, R5 // 855fb0e1 SLL R5, R6, R7 // 1675a0e1 SLL.S R5, R6, R7 // 1675b0e1 SLL R5, R7 // 1775a0e1
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 15 20:51:01 UTC 2023 - 69K bytes - Viewed (0) -
src/cmd/internal/obj/mips/asm0.go
break case 1: /* mov r1,r2 ==> OR r1,r0,r2 */ a := AOR if p.As == AMOVW && c.ctxt.Arch.Family == sys.MIPS64 { // on MIPS64, most of the 32-bit instructions have unpredictable behavior, // but SLL is special that the result is always sign-extended to 64-bit. a = ASLL } o1 = OP_RRR(c.oprrr(a), p.From.Reg, REGZERO, p.To.Reg) case 2: /* add/sub r1,[r2],r3 */ r := p.Reg
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 16 17:46:09 UTC 2024 - 53.6K bytes - Viewed (0) -
src/cmd/internal/obj/loong64/asm.go
case 8: // mov soreg, r r := int(p.From.Reg) if r == 0 { r = int(o.param) } v := c.regoff(&p.From) o1 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(r), uint32(p.To.Reg)) case 9: // sll r1,[r2],r3 if p.As != ACLO && p.As != ACLZ { r := int(p.Reg) if r == 0 { r = int(p.To.Reg) } o1 = OP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(r), uint32(p.To.Reg))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 61.8K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/obj.go
// Rotation instructions are supported natively. return []*instruction{ins} } switch ins.as { case AROL, AROLW, AROR, ARORW: // ROL -> OR (SLL x y) (SRL x (NEG y)) // ROR -> OR (SRL x y) (SLL x (NEG y)) sllOp, srlOp := ASLL, ASRL if ins.as == AROLW || ins.as == ARORW { sllOp, srlOp = ASLLW, ASRLW } shift1, shift2 := sllOp, srlOp
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sun Apr 07 03:32:27 UTC 2024 - 77K bytes - Viewed (0) -
src/cmd/internal/obj/arm/asm5.go
rel.Siz = 0 rel.Type = objabi.R_CALLIND case 8: /* sll $c,[R],R -> mov (R<<$c),R */ c.aclass(&p.From) o1 = c.oprrr(p, p.As, int(p.Scond)) r := int(p.Reg) if r == 0 { r = int(p.To.Reg) } o1 |= (uint32(r) & 15) << 0 o1 |= uint32((c.instoffset & 31) << 7) o1 |= (uint32(p.To.Reg) & 15) << 12 case 9: /* sll R,[R],R -> mov (R<<R),R */ o1 = c.oprrr(p, p.As, int(p.Scond))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 15 20:51:01 UTC 2023 - 79.4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64Ops.go
{name: "MSUB", argLength: 3, reg: gp31, asm: "MSUB"}, // +arg0 - (arg1 * arg2) {name: "MSUBW", argLength: 3, reg: gp31, asm: "MSUBW"}, // +arg0 - (arg1 * arg2), 32-bit // shifts {name: "SLL", argLength: 2, reg: gp21, asm: "LSL"}, // arg0 << arg1, shift amount is mod 64 {name: "SLLconst", argLength: 1, reg: gp11, asm: "LSL", aux: "Int64"}, // arg0 << auxInt, auxInt should be in the range 0 to 63.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 58.8K bytes - Viewed (0)