// LDTRH <Wt>, [<Xn|SP>{, #<simm>}]
	{0xffe00c00, 0x78400800, LDTRH, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil},
	// LDTRSB <Wt>, [<Xn|SP>{, #<simm>}]
	{0xffe00c00, 0x38c00800, LDTRSB, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil},
	// LDTRSB <Xt>, [<Xn|SP>{, #<simm>}]
	{0xffe00c00, 0x38800800, LDTRSB, instArgs{arg_Xt, arg_Xns_mem_optional_imm9_1_signed}, nil},
	// LDTRSH <Wt>, [<Xn|SP>{, #<simm>}]

{"Name":"LDR (immediate, SIMD&FP)","Bits":"11:2|1|1|1|1|0|0|01:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"LDR <Dt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
{"Name":"LDR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|11:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 128-bit variant","Syntax":"LDR <Qt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},

	return op | (d&31)<<21 | (a&31)<<16 | (sbit&1)<<15 | (simm&0xF)<<11
}

/* VA-form 3-register + SHB operands */
func AOP_IRRR(op uint32, d uint32, a uint32, b uint32, simm uint32) uint32 {
	return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (simm&0xF)<<6
}

/* VX-form 1-register + SIM operands */
func AOP_IR(op uint32, d uint32, simm uint32) uint32 {

	"ς":                          "\u03c2",
	"∼":                             "\u223c",
	"⩪":                          "\u2a6a",
	"≃":                            "\u2243",
	"≃":                           "\u2243",
	"⪞":                            "\u2a9e",
	"⪠":                           "\u2aa0",
	"⪝":                            "\u2a9d",

		"sigmav;":                          '\U000003C2',
		"sim;":                             '\U0000223C',
		"simdot;":                          '\U00002A6A',
		"sime;":                            '\U00002243',
		"simeq;":                           '\U00002243',
		"simg;":                            '\U00002A9E',
		"simgE;":                           '\U00002AA0',
		"siml;":                            '\U00002A9D',

				ab.Put1(byte(p.From.Offset))

			case Zevex_i_rm_k_r:
				imm, from, kmask, to := unpackOps4(p)
				ab.evex = newEVEXBits(z, &o.op)
				ab.asmevex(ctxt, p, from, nil, to, kmask)
				ab.asmand(ctxt, cursym, p, from, to)
				ab.Put1(byte(imm.Offset))

			case Zevex_i_rm_v_r:
				imm, from, from3, to := unpackOps4(p)
				ab.evex = newEVEXBits(z, &o.op)

			esize = 32
		case ARNG_2D:
			imax = 127
			esize = 64
		}

		imm := 0
		switch p.As {
		case AVUSHR, AVSRI, AVUSRA:
			imm = esize*2 - shift
			if imm < esize || imm > imax {
				c.ctxt.Diag("shift out of range: %v", p)
			}
		case AVSHL, AVSLI:
			imm = esize + shift
			if imm > imax {
				c.ctxt.Diag("shift out of range: %v", p)
			}
		default:

saxo

// sbi : 2015-03-12 STATE BANK OF INDIA
sbi

// sbs : 2014-11-07 ShortDot SA
sbs

// sca : 2014-03-13 SVENSKA CELLULOSA AKTIEBOLAGET SCA (publ)
sca

// scb : 2014-02-20 The Siam Commercial Bank Public Company Limited ("SCB")
scb

// schaeffler : 2015-08-06 Schaeffler Technologies AG & Co. KG
schaeffler

// schmidt : 2014-04-03 SCHMIDT GROUPE S.A.S.
schmidt

ryption-Iv":"WiqEFE5CDv/u8Z5JXqrSkC3RBDCvMw6=","X-Minio-Internal-Server-Side-Encryption-S3-Kms-Key-Id":"my-minio-key","X-Minio-Internal-Server-Side-Encryption-S3-Kms-Sealed-Key":"IAAfAMJ5CCL6tpT53w9o+W0oZ3gfRXIGW8rQRyCMo+Xukr67/XRy5fX+GUxbG8uhJBWS+SimQ==","X-Minio-Internal-Server-Side-Encryption-S3-Sealed-Key":"IAAfAMpAbRfgcSKkLKXB+HnNdvexQfHmBm2YPric5+ECRe8dW8GrSVqDWgY4Kv==","X-Minio-Internal-Server-Side-Encryption-Seal-Algorithm":"DAREv2-HMAC-SHA256","content-type":"application/octet-stream"}}...