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Results 1 - 10 of 28 for sval16 (0.31 sec)
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tensorflow/compiler/mlir/lite/experimental/tac/tests/get-alternative-subgraph.mlir
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 09:41:17 UTC 2024 - 20.1K bytes - Viewed (0) -
test/codegen/shift.go
func provedUnsignedShiftLeft(val64 uint64, val32 uint32, val16 uint16, val8 uint8, shift int) (r1 uint64, r2 uint32, r3 uint16, r4 uint8) { if shift >= 0 && shift < 64 { // arm64:"LSL",-"CSEL" r1 = val64 << shift } if shift >= 0 && shift < 32 { // arm64:"LSL",-"CSEL" r2 = val32 << shift } if shift >= 0 && shift < 16 { // arm64:"LSL",-"CSEL" r3 = val16 << shift } if shift >= 0 && shift < 8 {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue May 21 18:53:43 UTC 2024 - 12.7K bytes - Viewed (0) -
docs/bucket/replication/setup_ilm_expiry_replication.sh
echo "BUG: Transition rule on sitea seems to be overwritten" exit 1 fi ## Check replication of edit of prefix, tags and status of ILM Expiry Rules ./mc ilm rule edit --id "${id}" --prefix "newprefix" --tags "ntag1=nval1&ntag2=nval2" --disable sitea/bucket sleep 30s nprefix=$(./mc ilm rule list siteb/bucket --json | jq '.config.Rules[0].Filter.And.Prefix' | sed 's/"//g')
Registered: Sun Jun 16 00:44:34 UTC 2024 - Last Modified: Sat May 18 18:19:01 UTC 2024 - 12.8K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/experimental/tac/tests/device-transform-gpu.mlir
// CHECK: %[[VAL_5:.*]] = "tfl.reshape"(%[[VAL_0]], %[[VAL_2]]) : (tensor<1xf32>, tensor<4xi32>) -> tensor<1x1x1x1xf32> // CHECK: %[[VAL_6:.*]] = "tfl.reshape"(%[[VAL_1]], %[[VAL_2]]) : (tensor<1xf32>, tensor<4xi32>) -> tensor<1x1x1x1xf32> // CHECK: %[[VAL_7:.*]] = "tfl.concatenation"(%[[VAL_5]], %[[VAL_6]]) <{axis = 3 : i32, fused_activation_function = "NONE"}> : (tensor<1x1x1x1xf32>, tensor<1x1x1x1xf32>) -> tensor<1x1x1x2xf32>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 09:41:17 UTC 2024 - 15.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteAMD64splitload.go
// cond: vo.Val() != 0 // result: (CMPWconst (MOVWload {sym} [vo.Off()] ptr mem) [vo.Val16()]) for { vo := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 mem := v_1 if !(vo.Val() != 0) { break } v.reset(OpAMD64CMPWconst) v.AuxInt = int16ToAuxInt(vo.Val16()) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = int32ToAuxInt(vo.Off())
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Jan 19 22:42:34 UTC 2023 - 21.4K bytes - Viewed (0) -
operator/pkg/tpath/tree_test.go
Registered: Fri Jun 14 15:00:06 UTC 2024 - Last Modified: Mon Jul 25 19:30:47 UTC 2022 - 15.6K bytes - Viewed (0) -
src/cmd/compile/internal/types2/stmt.go
case v == nil && sValue != nil: check.softErrorf(sValue, InvalidIterVar, "range over %s permits only one iteration variable", &x) case sExtra != nil: check.softErrorf(sExtra, InvalidIterVar, "range clause permits at most two iteration variables") case isFunc && ((k == nil) != (sKey == nil) || (v == nil) != (sValue == nil)): var count string switch { case k == nil:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 30 19:19:55 UTC 2024 - 30.7K bytes - Viewed (0) -
platforms/software/dependency-management/src/test/groovy/org/gradle/api/internal/artifacts/ivyservice/resolveengine/result/ComponentSelectorSerializerTest.groovy
when: ModuleComponentSelector result1 = serialize(selector1, serializer) ModuleComponentSelector result2 = serialize(selector2, serializer) ModuleComponentSelector result3 = serialize(selector3, serializer) then: result1.attributes == AttributeTestUtil.attributes("foo": "val1")
Registered: Wed Jun 12 18:38:38 UTC 2024 - Last Modified: Tue Oct 10 21:10:11 UTC 2023 - 11.8K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/experimental/tac/tests/pick-subgraphs.mlir
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 09:41:17 UTC 2024 - 24.3K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/experimental/tac/tests/fold-constants-to-subgraph.mlir
// PARTIAL: return %[[VAL_5]] : tensor<1x384x32xf32> // PARTIAL: } // PARTIAL: func @arg_reuse_test_2(%[[VAL_6:.*]]: tensor<4x384x32xf32>, %[[VAL_7:.*]]: tensor<3xi32>, %[[VAL_8:.*]]: tensor<3xi32>) -> tensor<1x384x32xf32> attributes {tac.interface_name = "func2"} {
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 09:41:17 UTC 2024 - 10.5K bytes - Viewed (0)