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Results 1 - 2 of 2 for VL1RV (0.02 seconds)

  2. github.com/golang/go

    src/cmd/asm/internal/asm/testdata/riscv64validation.s 

    	VSOXSEG2EI8V	V3, V2, (V1)			// ERROR "expected integer register in rs1 position"
	VSOXSEG2EI8V	V3, X11, V0, (X10)		// ERROR "expected vector register in vs2 position"
	VL1RV		(X10), X10			// ERROR "expected vector register in vd position"
	VL1RV		(V1), V3			// ERROR "expected integer register in rs1 position"
	VS1RV		X11, (X11)			// ERROR "expected vector register in vs1 position"
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Thu Nov 13 12:17:37 GMT 2025
    - 42.1K bytes
    - Click Count (0)
  3. github.com/golang/go

    src/cmd/asm/internal/asm/testdata/riscv64error.s 

    	VSUXSEG2EI8V	V3, V2, V1, (X10)		// ERROR "invalid vector mask register"
	VLOXSEG2EI8V	(X10), V2, V1, V3		// ERROR "invalid vector mask register"
	VSOXSEG2EI8V	V3, V2, V1, (X10)		// ERROR "invalid vector mask register"
	VL1RV		(X10), V0, V3			// ERROR "too many operands for instruction"
	VS1RV		V3, V0, (X11)			// ERROR "too many operands for instruction"
	VADDVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Wed Apr 01 04:17:57 GMT 2026
    - 27.2K bytes
    - Click Count (0)
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