SUBC	R1, R2                // b90b0021
	SUBC	$1, R1, R2            // ec21ffff00db
	SUBC	R2, R3, R4            // b9eb2043
	SUBW	R3, R4                // 1b43
	SUBW	R3, R4, R5            // b9f93054
	SUBW	$8192, R1             // c21500002000
	SUBW	$8192, R1, R2         // 1821c22500002000
	MULLW	R6, R7                // b91c0076
	MULLW	R6, R7, R8            // b9040087b91c0086

	SLLW	X5, X6, X7				// bb135300
	SRLW	X5, X6, X7				// bb535300
	SUBW	X5, X6, X7				// bb035340
	SRAW	X5, X6, X7				// bb535340
	ADDIW	$1, X6					// 1b031300
	SLLIW	$1, X6					// 1b131300
	SRLIW	$1, X6					// 1b531300
	SRAIW	$1, X6					// 1b531340
	ADDW	X5, X7					// bb835300
	SLLW	X5, X7					// bb935300
	SRLW	X5, X7					// bbd35300
	SUBW	X5, X7					// bb835340
	SRAW	X5, X7					// bbd35340

	LGDR	F0, R3
	WORD	$0xC0298009	//iilf	%r2,2148095317
	BYTE	$0x55
	BYTE	$0x55
	RISBGNZ	$32, $63, $32, R3, R1
	SUBW	R1, R2
	RISBGNZ	$58, $63, $50, R2, R3
	BYTE	$0x18	//lr	%r5,%r1
	BYTE	$0x51
	MOVD	$·powtabi<>+0(SB), R12
	WORD	$0xE303C000	//llgc	%r0,0(%r3,%r12)
	BYTE	$0x00
	BYTE	$0x90
	SUBW	$0x1A0000, R5
	SLD	$3, R0, R3
	MOVD	$·powtm<>+0(SB), R4
	MOVH	$0x0, R8
	ANDW	$0x7FF00000, R2
	ORW	R5, R1

	STXRH R12, (R3), R8                        // 6c7c0848
	SUBW R20.UXTW<<2, R23, R19                 // f34a344b
	SUB R5.SXTW<<2, R1, R26                    // 3ac825cb
	SUB $(1923<<12), R4, R27                   // SUB $7876608, R4, R27         // 9b0c5ed1
	SUBW $(1923<<12), R4, R27                  // SUBW $7876608, R4, R27        // 9b0c5e51
	SUBW R12<<29, R7, R8                       // e8740c4b

(SUB <t> (MOVDconst [val]) y) && is32Bit(-val) => (NEG (ADDI <t> [-val] y))

// Subtraction of zero.
(SUB  x (MOVDconst [0])) => x
(SUBW x (MOVDconst [0])) => (ADDIW [0] x)

// Subtraction from zero.
(SUB  (MOVDconst [0]) x) => (NEG x)
(SUBW (MOVDconst [0]) x) => (NEGW x)

// Fold negation into subtraction.
(NEG (SUB x y)) => (SUB y x)

		{name: "NEGW", argLength: 1, reg: gp11, asm: "NEGW"},                  // -arg0 of 32 bits, sign extended to 64 bits
		{name: "SUB", argLength: 2, reg: gp21, asm: "SUB"},                    // arg0 - arg1
		{name: "SUBW", argLength: 2, reg: gp21, asm: "SUBW"},                  // 32 low bits of arg 0 - 32 low bits of arg 1, sign extended to 64 bits

		// M extension. H means high (i.e., it returns the top bits of

	"STI",
	"STMXCSR",
	"STOSB",
	"STOSL",
	"STOSQ",
	"STOSW",
	"STRL",
	"STRQ",
	"STRW",
	"SUBB",
	"SUBL",
	"SUBPD",
	"SUBPS",
	"SUBQ",
	"SUBSD",
	"SUBSS",
	"SUBW",
	"SWAPGS",
	"SYSCALL",
	"SYSENTER",
	"SYSENTER64",
	"SYSEXIT",
	"SYSEXIT64",
	"SYSRET",
	"TESTB",
	"TESTL",
	"TESTQ",
	"TESTW",
	"TPAUSE",
	"TZCNTL",
	"TZCNTQ",

	ADDSW	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
	SUB	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
	SUBW	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
	SUBS	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"

	VEOR	V0.B16, V2.B16, V0.B16
	VEOR	V4.B16, V6.B16, V4.B16
	VEOR	V4.B16, V0.B16, V0.B16

	VMOV	V0.D[0], R0
	RET

TEXT runtime·procyield(SB),NOSPLIT,$0-0
	MOVWU	cycles+0(FP), R0
again:
	YIELD
	SUBW	$1, R0
	CBNZ	R0, again
	RET

// Save state of caller into g->sched,
// but using fake PC from systemstack_switch.
// Must only be called from functions with no locals ($0)