// ppc64x:-".*RLWINM",-".*RLDICR",".*CLRLSLDI"
	f := tab[byte(v)^b]
	// ppc64x:-".*RLWINM",-".*RLDICR",".*CLRLSLDI"
	f += tab[byte(v)&b]
	// ppc64x:-".*RLWINM",-".*RLDICR",".*CLRLSLDI"
	f += tab[byte(v)|b]
	// ppc64x:-".*RLWINM",-".*RLDICR",".*CLRLSLDI"
	f += tab[uint16(v)&h]
	// ppc64x:-".*RLWINM",-".*RLDICR",".*CLRLSLDI"
	f += tab[uint16(v)^h]

More recently, Go opcodes were added which map directly onto the PPC64 opcodes. It is
recommended to use the newer opcodes to avoid confusion.

	RLDICL $0,R4,$15,R6		=>	rldicl r6,r4,0,15
	RLDICR $0,R4,$15,R6		=>	rldicr r6.r4,0,15

# Register naming

1. Special register usage in Go asm

The following registers should not be modified by user Go assembler code.

	MOVD	m_curg(R21), R6
	CMP	g, R6
	BNE	noswitch

	MOVD	m_g0(R21), R7
	MOVD	(g_sched+gobuf_sp)(R7), R1	// Set SP to g0 stack

noswitch:
	SUB	$16, R1                 // Space for results
	RLDICR	$0, R1, $59, R1         // Align for C code
	MOVD	R12, CTR
	MOVD	R1, R4

	// Store g on gsignal's stack, so if we receive a signal
	// during VDSO code we can find the g.

loadge16:
	ANDCC $15, R5, R9 // Find byte offset of sep
	ADD   R9, R6, R10 // Add sep len
	CMP   R10, $16    // Check if sep len+offset > 16
	BGT   sepcross16  // Sep crosses 16 byte boundary

	RLDICR $0, R5, $59, R8 // Adjust addr to 16 byte container
	VLOADSWAP(R8, R0, V0, V0) // Load 16 bytes @R8 into V0
	SLD    $3, R9          // Set up shift count for VSLO
	MTVSRD R9, V8         // Set up shift count for VSLO

			v.AuxInt = int64ToAuxInt(encodePPC64RotateMask(0, m, 64))
			v.AddArg(n)
			return true
		}
		break
	}
	// match: (AND x:(MOVDconst [m]) n)
	// cond: m != 0 && isPPC64ValidShiftMask(^m)
	// result: (RLDICR [encodePPC64RotateMask(0,m,64)] n)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if x.Op != OpPPC64MOVDconst {
				continue
			}
			m := auxIntToInt64(x.AuxInt)

#else
	VSLDOI	$4,V8,zeroes,V8
#endif

#ifdef BYTESWAP_DATA
	MOVD    $·byteswapcons(SB),R3
	LVX	(R3),byteswap
#endif

	CMPU	R5,$256		// length of bytes
	BLT	short

	RLDICR	$0,R5,$56,R6 // chunk to process

	// First step for larger sizes
l1:	MOVD	$32768,R7
	MOVD	R7,R9
	CMP	R6,R7   // compare R6, R7 (MAX SIZE)
	BGT	top	// less than MAX, just do remainder
	MOVD	R6,R7
top:

		{name: "RLDICLCC", argLength: 1, reg: gp11, asm: "RLDICLCC", aux: "Int64", typ: "(Int, Flags)"}, // Auxint is encoded similarly to RLWINM, but only MB and SH are valid. ME is always 63. Sets CC.
		{name: "RLDICR", argLength: 1, reg: gp11, asm: "RLDICR", aux: "Int64"},                          // Likewise, but only ME and SH are valid. MB is always 0.

		{name: "CNTLZD", argLength: 1, reg: gp11, asm: "CNTLZD"},                          // count leading zeros