ADDS	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
	ADDSW	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
	SUB	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
	SUBW	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"

	MOVW	R4, 65536(R5)			// 1e020014de971000c4038029
	MOVW	R4, 4096(R5)  			// 3e000014de971000c4038029
	MOVWU	R4, 65536(R5)			// 1e020014de971000c4038029
	MOVWU	R4, 4096(R5)			// 3e000014de971000c4038029
	MOVV	R4, 65536(R5)			// 1e020014de971000c403c029
	MOVV	R4, 4096(R5)			// 3e000014de971000c403c029
	MOVB	R4, 65536(R5)			// 1e020014de971000c4030029
	MOVB	R4, 4096(R5)			// 3e000014de971000c4030029

	{"(16)(R7)", "16(R7)"},
	{"(8)(g)", "8(g)"},
	{"(CTR)", "(CTR)"},
	{"(R0)", "(R0)"},
	{"(R3)", "(R3)"},
	{"(R4)", "(R4)"},
	{"(R5)", "(R5)"},
	{"(R5)(R6*1)", "(R5)(R6*1)"},
	{"(R5+R6)", "(R5)(R6)"},
	{"-1(R4)", "-1(R4)"},
	{"-1(R5)", "-1(R5)"},
	{"6(PC)", "6(PC)"},
	{"CR7", "CR7"},
	{"CTR", "CTR"},
	{"VS0", "VS0"},
	{"VS1", "VS1"},
	{"VS2", "VS2"},
	{"VS3", "VS3"},

	SLW	R2, R3, R6              // eb63200000df
	SLD	$4, R3, R6              // eb630004000d
	SLD	R2, R3, R6              // eb632000000d
	SRAD	$4, R5, R8              // eb850004000a
	SRAD	R3, R5, R8              // eb853000000a
	SRAW	$4, R5, R8              // eb85000400dc
	SRAW	R3, R5, R8              // eb85300000dc
	RLL	R1, R2, R3              // eb321000001d
	RLL	$4, R2, R3              // eb320004001d

	ADDV	R4, R5			// a5901000
	AND	R4, R5			// a5901400
	NEGW	R4, R5			// 05101100
	NEGV	R4, R5			// 05901100
	SLL	R4, R5			// a5101700
	SLL	R4, R5, R6		// a6101700
	SRL	R4, R5			// a5901700
	SRL	R4, R5, R6	 	// a6901700
	SRA	R4, R5			// a5101800
	SRA	R4, R5, R6	 	// a6101800
	ROTR	R4, R5			// a5101b00
	ROTR	R4, R5, R6		// a6101b00
	SLLV	R4, R5			// a5901800
	SLLV	R4, R5, R6		// a6901800
	ROTRV	R4, R5			// a5901b00

//	{
//		outcode(int($1), &$2, int($4), &$6);
//	}
	ADD	R5, R9, R10	// 01255020
	ADDU	R13, R14, R19	// 01cd9821
	ADDV	R5, R9, R10	// 0125502c
	ADDVU	R13, R14, R19	// 01cd982d

//	LADDW imm ',' sreg ',' rreg
//	{
//		outcode(int($1), &$2, int($4), &$6);
//	}
	ADD	$15176, R14, R9	// 21c93b48
	ADD	$-9, R5, R8	// 20a8fff7
	ADDU	$10, R9, R9	// 2529000a
	ADDV	$15176, R14, R9	// 61c93b48

	CMNW $(2<<12), R5                          // CMNW $8192, R5                // bf084031
	CMN $(8<<12), R12                          // CMN $32768, R12               // 9f2140b1
	CMN R6->0, R3                              // 7f0086ab
	CMN R6, R3                                 // 7f0006ab
	CMNW R30, R5                               // bf001e2b
	CMNW $2, R5                                // bf080031

	XTABU	R0->24, R2         // ERROR "illegal shift"
	XTAHU	R0@>1, R2          // ERROR "illegal shift"
	XTAB	R0>>8, R5, R2      // ERROR "illegal shift"
	XTAH	R0<<16, R5, R2     // ERROR "illegal shift"
	XTABU	R0->24, R5, R2     // ERROR "illegal shift"
	XTAHU	R0@>1, R5, R2      // ERROR "illegal shift"
	AND.W	R0, R1             // ERROR "invalid .W suffix"
	ORR.P	R2, R3, R4         // ERROR "invalid .P suffix"

	CNTTZDM R2, R3, R1                      // 7c411c76
	DCFFIXQQ V1, F2                         // fc400fc4
	DCTFIXQQ F2, V3                         // fc6117c4
	LXVKQ $0, VS33                          // f03f02d1
	LXVP 12352(R5), VS6                     // 18c53040
	LXVPX (R1)(R2), VS4                     // 7c820a9a
	LXVRBX (R1)(R2), VS4                    // 7c82081a
	LXVRDX (R1)(R2), VS4                    // 7c8208da

<p>
Load- and store-multiple instructions operate on a range of registers.
The range of registers is specified by a start register and an end register.
For example, <code>LMG</code> <code>(R9),</code> <code>R5,</code> <code>R7</code> would load
<code>R5</code>, <code>R6</code> and <code>R7</code> with the 64-bit values at
<code>0(R9)</code>, <code>8(R9)</code> and <code>16(R9)</code> respectively.
</p>

<p>