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Results 1 - 6 of 6 for ROR (0.01 sec)

  1. test/codegen/arithmetic.go

    	// arm64:"MOVD\t[$]-6148914691236517205","MOVD\t[$]3074457345618258602","MUL","ROR",-"DIV"
    	// arm:"MUL","CMP\t[$]715827882",-".*udiv"
    	// ppc64x:"MULLD","ROTL\t[$]63"
    	even := n%6 == 0
    
    	// amd64:"MOVQ\t[$]-8737931403336103397","IMULQ",-"ROLQ",-"DIVQ"
    	// 386:"IMUL3L\t[$]678152731",-"ROLL",-"DIVQ"
    	// arm64:"MOVD\t[$]-8737931403336103397","MUL",-"ROR",-"DIV"
    	// arm:"MUL","CMP\t[$]226050910",-".*udiv"
    	// ppc64x:"MULLD",-"ROTL"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 17 15:28:00 UTC 2024
    - 15.2K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/riscv64.s

    	ROLW	X9, X10, X11				// bb159560 or b30f9040bb5ff501bb159500b3e5bf00
    	ROLW	X9, X10					// 3b159560 or b30f9040bb5ff5013b15950033e5af00
    	ROR	X10, X11, X12				// 33d6a560 or b30fa040b39ff50133d6a50033e6cf00
    	ROR	X10, X11				// b3d5a560 or b30fa040b39ff501b3d5a500b3e5bf00
    	ROR	$63, X11				// 93d5f563 or 93dff50393951500b3e5bf00
    	RORI	$63, X11, X12				// 13d6f563 or 93dff5031396150033e6cf00
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Mar 22 04:42:21 UTC 2024
    - 16.7K bytes
    - Viewed (0)
  3. src/crypto/sha256/sha256block_amd64.s

    	XORL    g, y2;                       \ // y2 = CH = ((f^g)&e)^g		// CH
    	;                                    \
    	VPXOR   XTMP2, XTMP3, XTMP3;         \ // XTMP3 = W[-15] ror 7 ^ W[-15] ror 18
    	XORL    T1, y1;                      \ // y1 = (a>>22) ^ (a>>13) ^ (a>>2)		// S0
    	MOVL    a, T1;                       \ // T1 = a						// MAJB
    	ANDL    c, T1;                       \ // T1 = a&c						// MAJB
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 04 17:29:44 UTC 2024
    - 47.3K bytes
    - Viewed (0)
  4. test/codegen/mathbits.go

    	return bits.RotateLeft8(n, s)
    }
    
    func RotateLeftVariable(n uint, m int) uint {
    	// amd64:"ROLQ"
    	// arm64:"ROR"
    	// ppc64x:"ROTL"
    	// s390x:"RLLG"
    	// wasm:"I64Rotl"
    	return bits.RotateLeft(n, m)
    }
    
    func RotateLeftVariable64(n uint64, m int) uint64 {
    	// amd64:"ROLQ"
    	// arm64:"ROR"
    	// ppc64x:"ROTL"
    	// s390x:"RLLG"
    	// wasm:"I64Rotl"
    	return bits.RotateLeft64(n, m)
    }
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 18:51:17 UTC 2024
    - 19.6K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go

    		{name: "ROLW", argLength: 2, reg: gp21, asm: "ROLW"},                  // rotate left least significant word of arg0 by (arg1 & 31), sign extended
    		{name: "ROR", argLength: 2, reg: gp21, asm: "ROR"},                    // rotate right arg0 by (arg1 & 63)
    		{name: "RORI", argLength: 1, reg: gp11, asm: "RORI", aux: "Int64"},    // rotate right arg0 by auxint, shift amount 0-63
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 30.7K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/_gen/RISCV64.rules

    (XOR (MOVDconst [val]) x) && is32Bit(val) => (XORI [val] x)
    (ROL  x (MOVDconst [val])) => (RORI  [int64(int8(-val)&63)] x)
    (ROLW x (MOVDconst [val])) => (RORIW [int64(int8(-val)&31)] x)
    (ROR  x (MOVDconst [val])) => (RORI  [int64(val&63)] x)
    (RORW x (MOVDconst [val])) => (RORIW [int64(val&31)] x)
    (SLL  x (MOVDconst [val])) => (SLLI [int64(val&63)] x)
    (SRL  x (MOVDconst [val])) => (SRLI [int64(val&63)] x)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 40.3K bytes
    - Viewed (0)
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