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Results 1 - 10 of 10 for ADDV (0.18 sec)

  1. src/runtime/duff_loong64.s

    	ADDV	$8, R20
    	MOVV	R0, (R20)
    	ADDV	$8, R20
    	MOVV	R0, (R20)
    	ADDV	$8, R20
    	MOVV	R0, (R20)
    	ADDV	$8, R20
    	MOVV	R0, (R20)
    	ADDV	$8, R20
    	MOVV	R0, (R20)
    	ADDV	$8, R20
    	MOVV	R0, (R20)
    	ADDV	$8, R20
    	MOVV	R0, (R20)
    	ADDV	$8, R20
    	MOVV	R0, (R20)
    	ADDV	$8, R20
    	MOVV	R0, (R20)
    	ADDV	$8, R20
    	MOVV	R0, (R20)
    	ADDV	$8, R20
    	MOVV	R0, (R20)
    	ADDV	$8, R20
    	MOVV	R0, (R20)
    	ADDV	$8, R20
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:04:21 UTC 2023
    - 11.9K bytes
    - Viewed (0)
  2. src/runtime/asm_mips64x.s

    	/* copy arguments to stack */		\
    	MOVV	stackArgs+16(FP), R1;			\
    	MOVWU	stackArgsSize+24(FP), R2;			\
    	MOVV	R29, R3;				\
    	ADDV	$8, R3;			\
    	ADDV	R3, R2;				\
    	BEQ	R3, R2, 6(PC);				\
    	MOVBU	(R1), R4;			\
    	ADDV	$1, R1;			\
    	MOVBU	R4, (R3);			\
    	ADDV	$1, R3;			\
    	JMP	-5(PC);				\
    	/* call function */			\
    	MOVV	f+8(FP), REGCTXT;			\
    	MOVV	(REGCTXT), R4;			\
    	PCDATA  $PCDATA_StackMapIndex, $0;	\
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Nov 06 19:45:59 UTC 2023
    - 24.3K bytes
    - Viewed (0)
  3. test/codegen/mathbits.go

    	// amd64:"NEGL","ADCQ","SBBQ","NEGQ"
    	// loong64: "ADDV", "SGTU"
    	// ppc64x: "ADDC", "ADDE", "ADDZE"
    	// s390x:"ADDE","ADDC\t[$]-1,"
    	// mips64:"ADDV","SGTU"
    	// riscv64: "ADD","SLTU"
    	return bits.Add(x, 7, ci)
    }
    
    func AddZ(x, y uint) (r, co uint) {
    	// arm64:"ADDS","ADC",-"ADCS",-"ADD\t",-"CMP"
    	// amd64:"ADDQ","SBBQ","NEGQ",-"NEGL",-"ADCQ"
    	// loong64: "ADDV", "SGTU"
    	// ppc64x: "ADDC", -"ADDE", "ADDZE"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 18:51:17 UTC 2024
    - 19.6K bytes
    - Viewed (0)
  4. src/runtime/asm_loong64.s

    	NO_LOCAL_POINTERS;			\
    	/* copy arguments to stack */		\
    	MOVV	arg+16(FP), R4;			\
    	MOVWU	argsize+24(FP), R5;			\
    	MOVV	R3, R12;				\
    	ADDV	$8, R12;			\
    	ADDV	R12, R5;				\
    	BEQ	R12, R5, 6(PC);				\
    	MOVBU	(R4), R6;			\
    	ADDV	$1, R4;			\
    	MOVBU	R6, (R12);			\
    	ADDV	$1, R12;			\
    	JMP	-5(PC);				\
    	/* set up argument registers */		\
    	MOVV	regArgs+40(FP), R25;		\
    	JAL	·unspillArgs(SB);		\
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon May 13 15:04:25 UTC 2024
    - 26.5K bytes
    - Viewed (0)
  5. src/cmd/asm/internal/asm/testdata/mips64.s

    //	}
    	ADD	R5, R9, R10	// 01255020
    	ADDU	R13, R14, R19	// 01cd9821
    	ADDV	R5, R9, R10	// 0125502c
    	ADDVU	R13, R14, R19	// 01cd982d
    
    //	LADDW imm ',' sreg ',' rreg
    //	{
    //		outcode(int($1), &$2, int($4), &$6);
    //	}
    	ADD	$15176, R14, R9	// 21c93b48
    	ADD	$-9, R5, R8	// 20a8fff7
    	ADDU	$10, R9, R9	// 2529000a
    	ADDV	$15176, R14, R9	// 61c93b48
    	ADDV	$-9, R5, R8	// 60a8fff7
    	ADDVU	$10, R9, R9	// 6529000a
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 12.4K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/_gen/LOONG64.rules

    (Select0 <t> (Add64carry x y c)) => (ADDV (ADDV <t> x y) c)
    (Select1 <t> (Add64carry x y c)) =>
    	(OR (SGTU <t> x s:(ADDV <t> x y)) (SGTU <t> s (ADDV <t> s c)))
    
    (Select0 <t> (Sub64borrow x y c)) => (SUBV (SUBV <t> x y) c)
    (Select1 <t> (Sub64borrow x y c)) =>
    	(OR (SGTU <t> s:(SUBV <t> x y) x) (SGTU <t> (SUBV <t> s c) s))
    
    // (x + y) / 2 with x>=y => (x - y) / 2 + y
    (Avg64u <t> x y) => (ADDV (SRLVconst <t> (SUBV <t> x y) [1]) y)
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:26:25 UTC 2023
    - 31.8K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go

    		// arg2 = address of the last element of src
    		// arg3 = mem
    		// auxint = alignment
    		// returns mem
    		//	MOVx	(R20), Rtmp
    		//	MOVx	Rtmp, (R21)
    		//	ADDV	$sz, R20
    		//	ADDV	$sz, R21
    		//	BGEU	Rarg2, R20, -4(PC)
    		{
    			name:      "LoweredMove",
    			aux:       "Int64",
    			argLength: 4,
    			reg: regInfo{
    				inputs:   []regMask{buildReg("R21"), buildReg("R20"), gp},
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:04:19 UTC 2023
    - 25.2K bytes
    - Viewed (0)
  8. src/cmd/compile/internal/ssa/_gen/MIPS64.rules

    (Mod8 x y) => (Select0 (DIVV (SignExt8to64 x) (SignExt8to64 y)))
    (Mod8u x y) => (Select0 (DIVVU (ZeroExt8to64 x) (ZeroExt8to64 y)))
    
    (Select0 <t> (Add64carry x y c)) => (ADDV (ADDV <t> x y) c)
    (Select1 <t> (Add64carry x y c)) =>
    	(OR (SGTU <t> x s:(ADDV <t> x y)) (SGTU <t> s (ADDV <t> s c)))
    
    (Select0 <t> (Sub64borrow x y c)) => (SUBV (SUBV <t> x y) c)
    (Select1 <t> (Sub64borrow x y c)) =>
    	(OR (SGTU <t> s:(SUBV <t> x y) x) (SGTU <t> (SUBV <t> s c) s))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jul 31 03:59:48 UTC 2023
    - 41.9K bytes
    - Viewed (0)
  9. src/runtime/sys_linux_loong64.s

    	MOVV	$1000, R6
    	MULVU	R6, R7, R7
    	MOVV	$1000000000, R6
    
    	DIVVU	R6, R7, R5	// ts->tv_sec
    	REMVU	R6, R7, R4	// ts->tv_nsec
    	MOVV	R5, 8(R3)
    	MOVV	R4, 16(R3)
    
    	// nanosleep(&ts, 0)
    	ADDV	$8, R3, R4
    	MOVV	R0, R5
    	MOVV	$SYS_nanosleep, R11
    	SYSCALL
    	RET
    
    // func gettid() uint32
    TEXT runtime·gettid(SB),NOSPLIT,$0-4
    	MOVV	$SYS_gettid, R11
    	SYSCALL
    	MOVW	R4, ret+0(FP)
    	RET
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Aug 25 20:58:13 UTC 2023
    - 14.2K bytes
    - Viewed (0)
  10. src/runtime/mkpreempt.go

    	mov := "MOVW"
    	movf := "MOVF"
    	add := "ADD"
    	sub := "SUB"
    	r28 := "R28"
    	regsize := 4
    	softfloat := "GOMIPS_softfloat"
    	if _64bit {
    		mov = "MOVV"
    		movf = "MOVD"
    		add = "ADDV"
    		sub = "SUBV"
    		r28 = "RSB"
    		regsize = 8
    		softfloat = "GOMIPS64_softfloat"
    	}
    
    	// Add integer registers R1-R22, R24-R25, R28
    	// R0 (zero), R23 (REGTMP), R29 (SP), R30 (g), R31 (LR) are special,
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Nov 20 17:19:36 UTC 2023
    - 15.3K bytes
    - Viewed (0)
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