Search Options

Results per page
Sort
Preferred Languages
Advance

Results 1 - 7 of 7 for rldcl (0.16 sec)

  1. src/cmd/internal/obj/ppc64/anames.go

    	"MULHDU",
    	"MULHDUCC",
    	"MULLD",
    	"MULLDCC",
    	"MULLDVCC",
    	"MULLDV",
    	"RFID",
    	"RLDMI",
    	"RLDMICC",
    	"RLDIMI",
    	"RLDIMICC",
    	"RLDC",
    	"RLDCCC",
    	"RLDCR",
    	"RLDCRCC",
    	"RLDICR",
    	"RLDICRCC",
    	"RLDCL",
    	"RLDCLCC",
    	"RLDICL",
    	"RLDICLCC",
    	"RLDIC",
    	"RLDICCC",
    	"CLRLSLDI",
    	"ROTL",
    	"ROTLW",
    	"SLBIA",
    	"SLBIE",
    	"SLBMFEE",
    	"SLBMFEV",
    	"SLBMTE",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Apr 01 18:50:29 UTC 2024
    - 6.7K bytes
    - Viewed (0)
  2. test/codegen/constants.go

    	// ppc64x: "MOVD\t[$]-1", "RLDC\tR[0-9]+, [$]44, [$]63,"
    	out[0] = 0xFFFFF00000000001
    	// ppc64x: "MOVD\t[$]-1", "RLDC\tR[0-9]+, [$]43, [$]63,"
    	out[1] = 0xFFFFF80000000001
    	// ppc64x: "MOVD\t[$]-1", "RLDC\tR[0-9]+, [$]43, [$]4,"
    	out[2] = 0x0FFFF80000000000
    	// ppc64x/power8: "MOVD\t[$]-1", "RLDC\tR[0-9]+, [$]33, [$]63,"
    	// ppc64x/power9: "MOVD\t[$]-1", "RLDC\tR[0-9]+, [$]33, [$]63,"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 05 14:03:32 UTC 2023
    - 1.1K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/_gen/PPC64latelower.rules

    (AND x:(MOVDconst [m]) n) && isPPC64ValidShiftMask(m) => (RLDICL [encodePPC64RotateMask(0,m,64)] n)
    (AND x:(MOVDconst [m]) n) && m != 0 && isPPC64ValidShiftMask(^m) => (RLDICR [encodePPC64RotateMask(0,m,64)] n)
    
    // If the RLDICL does not rotate its value, a shifted value can be merged.
    (RLDICL [em] x:(SRDconst [s] a)) && (em&0xFF0000) == 0 => (RLDICL [mergePPC64RLDICLandSRDconst(em, s)] a)
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 19:59:38 UTC 2024
    - 3.8K bytes
    - Viewed (0)
  4. test/codegen/bool.go

    	// amd64:"ANDL\t[$]1",-"SETB"
    	// ppc64x:"RLDICL",-"CMP",-"ISEL"
    	b := x&1 != 0
    	return c && b
    }
    
    func convertNeqBool32(x uint32) bool {
    	// ppc64x:"RLDICL",-"CMPW",-"ISEL"
    	return x&1 != 0
    }
    
    func convertEqBool32(x uint32) bool {
    	// ppc64x:"RLDICL",-"CMPW","XOR",-"ISEL"
    	return x&1 == 0
    }
    
    func convertNeqBool64(x uint64) bool {
    	// ppc64x:"RLDICL",-"CMP",-"ISEL"
    	return x&1 != 0
    }
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Nov 13 22:12:32 UTC 2023
    - 6.7K bytes
    - Viewed (0)
  5. src/runtime/asan_ppc64le.s

    	CMP	R10, g			// same g0?
    	BEQ	call			// already on g0
    	MOVD	(g_sched+gobuf_sp)(R10), R1 // switch R1
    call:
    	// prepare frame for C ABI
    	SUB	$32, R1			// create frame for callee saving LR, CR, R2 etc.
    	RLDCR	$0, R1, $~15, R1	// align SP to 16 bytes
    	MOVD	FARG, CTR		// address of function to be called
    	MOVD	R0, 0(R1)		// clear back chain pointer
    	BL	(CTR)
    	MOVD	$0, R0			// C code can clobber R0 set it back to 0
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Aug 26 18:13:33 UTC 2022
    - 2.8K bytes
    - Viewed (0)
  6. test/codegen/bits.go

    	// ppc64x: "RLDICR\t[$]0, R[0-9]*, [$]47, R"
    	io64[0] = io64[0] & 0xFFFFFFFFFFFF0000
    	// ppc64x: "RLDICL\t[$]0, R[0-9]*, [$]16, R"
    	io64[1] = io64[1] & 0x0000FFFFFFFFFFFF
    	// ppc64x: -"SRD", -"AND", "RLDICL\t[$]60, R[0-9]*, [$]16, R"
    	io64[2] = (io64[2] >> 4) & 0x0000FFFFFFFFFFFF
    	// ppc64x: -"SRD", -"AND", "RLDICL\t[$]36, R[0-9]*, [$]28, R"
    	io64[3] = (io64[3] >> 28) & 0x0000FFFFFFFFFFFF
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 7.8K bytes
    - Viewed (0)
  7. src/vendor/golang.org/x/crypto/internal/poly1305/sum_ppc64le.s

    	MULLD  h2, r1, t3;  \
    	ADDZE  t4, h0;      \
    	MULHDU r1, h1, t5;  \
    	MULLD  r1, h1, t4;  \
    	ADDC   t4, t2, t2;  \
    	ADDE   t5, t3, t3;  \
    	ADDC   h0, t2, t2;  \
    	MOVD   $-4, t4;     \
    	ADDZE  t3;          \
    	RLDICL $0, t2, $62, h2; \
    	AND    t2, t4, h0;  \
    	ADDC   t0, h0, h0;  \
    	ADDE   t3, t1, h1;  \
    	SLD    $62, t3, t4; \
    	SRD    $2, t2;      \
    	ADDZE  h2;          \
    	OR     t4, t2, t2;  \
    	SRD    $2, t3;      \
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Sat Mar 09 00:09:40 UTC 2024
    - 3.2K bytes
    - Viewed (0)
Back to top