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src/cmd/asm/internal/arch/arm.go
// one of the comparison instructions that require special handling. func IsARMCMP(op obj.As) bool { switch op { case arm.ACMN, arm.ACMP, arm.ATEQ, arm.ATST: return true } return false } // IsARMSTREX reports whether the op (as defined by an arm.A* constant) is // one of the STREX-like instructions that require special handling. func IsARMSTREX(op obj.As) bool { switch op {
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Wed Oct 23 15:18:14 UTC 2024 - 6.1K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64error.s
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Wed Jun 14 00:03:57 UTC 2023 - 8.9K bytes - Viewed (0) -
src/cmd/asm/internal/arch/loong64.go
return true } return false } // IsLoong64MUL reports whether the op (as defined by an loong64.A* constant) is // one of the MUL/DIV/REM instructions that require special handling. func IsLoong64MUL(op obj.As) bool { switch op { case loong64.AMUL, loong64.AMULU, loong64.AMULV, loong64.AMULVU, loong64.ADIV, loong64.ADIVU, loong64.ADIVV, loong64.ADIVVU,
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Mon Jul 29 02:47:00 UTC 2024 - 1.8K bytes - Viewed (0) -
src/cmd/asm/internal/arch/ppc64.go
// one of the CMP instructions that require special handling. func IsPPC64CMP(op obj.As) bool { switch op { case ppc64.ACMP, ppc64.ACMPU, ppc64.ACMPW, ppc64.ACMPWU, ppc64.AFCMPO, ppc64.AFCMPU: return true } return false } // IsPPC64NEG reports whether the op (as defined by an ppc64.A* constant) is // one of the NEG-like instructions that require special handling.
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Fri May 17 21:53:50 UTC 2024 - 2.2K bytes - Viewed (0) -
README.md
After downloading a binary release, visit https://go.dev/doc/install for installation instructions. #### Install From Source If a binary distribution is not available for your combination of operating system and architecture, visit https://go.dev/doc/install/source for source installation instructions. ### Contributing Go is the work of thousands of contributors. We appreciate your help!
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Mon Jul 22 17:45:27 UTC 2024 - 1.4K bytes - Viewed (0) -
src/cmd/asm/internal/arch/mips.go
// one of the CMP instructions that require special handling. func IsMIPSCMP(op obj.As) bool { switch op { case mips.ACMPEQF, mips.ACMPEQD, mips.ACMPGEF, mips.ACMPGED, mips.ACMPGTF, mips.ACMPGTD: return true } return false } // IsMIPSMUL reports whether the op (as defined by an mips.A* constant) is // one of the MUL/DIV/REM/MADD/MSUB instructions that require special handling.
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Wed Mar 04 19:06:44 UTC 2020 - 1.7K bytes - Viewed (0) -
futures/failureaccess/pom.xml
</goals> </execution> </executions> <configuration> <instructions> <Export-Package>com.google.common.util.concurrent.internal</Export-Package> <Bundle-DocURL>https://github.com/google/guava/</Bundle-DocURL> </instructions> </configuration> </plugin> <plugin> <artifactId>maven-javadoc-plugin</artifactId>
Registered: Fri Nov 01 12:43:10 UTC 2024 - Last Modified: Tue Oct 17 02:24:23 UTC 2023 - 3.3K bytes - Viewed (0) -
.github/ISSUE_TEMPLATE/10_contributor_bug_report.yml
name: Bug Report description: Create a report to help us improve labels: [ "a:bug", "to-triage" ] assignees: [ ] body: - type: markdown attributes: value: | Please follow the instructions below. We receive dozens of issues every week, so to stay productive, we will close issues that don't provide enough information.
Registered: Wed Nov 06 11:36:14 UTC 2024 - Last Modified: Mon Sep 09 14:48:49 UTC 2024 - 3K bytes - Viewed (0) -
docs/en/docs/management.md
## Team There's a team of people that help manage and maintain the project. 😎 They have different levels of permissions and [specific instructions](./management-tasks.md){.internal-link target=_blank}. Some of the tasks they can perform include: * Adding labels to PRs. * Editing PR titles. * Adding commits on top of PRs to tweak them.
Registered: Sun Nov 03 07:19:11 UTC 2024 - Last Modified: Wed Jul 31 14:09:15 UTC 2024 - 1.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips.s
MOVW R1, M1 // LMOVW mreg ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } MOVW M1, R1 MOVW M1, R1 // // integer operations // logical instructions // shift instructions // unary instructions // // LADDW rreg ',' sreg ',' rreg // { // outcode(int($1), &$2, int($4), &$6); // } ADD R1, R2, R3 // LADDW imm ',' sreg ',' rreg // {
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 6.7K bytes - Viewed (0)