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src/cmd/asm/internal/asm/testdata/riscv64error.s
// Copyright 2021 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. TEXT errors(SB),$0 MOV $errors(SB), (X5) // ERROR "address load must target register" MOV $8(SP), (X5) // ERROR "address load must target register" MOVB $8(SP), X5 // ERROR "unsupported address load" MOVH $8(SP), X5 // ERROR "unsupported address load"
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Sun Apr 07 03:32:27 GMT 2024 - 2.8K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips.s
// Copyright 2016 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // This input was created by taking the mips64 testcase and modified // by hand. #include "../../../../../runtime/textflag.h" TEXT foo(SB),DUPOK|NOSPLIT,$0 //inst: // // load ints and bytes // // LMOVW rreg ',' rreg // { // outcode(int($1), &$2, 0, &$4); // }
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Aug 08 12:17:12 GMT 2023 - 6.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64error.s
// Copyright 2016 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. TEXT errors(SB),$0 MOVL foo<>(SB)(AX), AX // ERROR "invalid instruction" MOVL (AX)(SP*1), AX // ERROR "invalid instruction" EXTRACTPS $4, X2, (BX) // ERROR "invalid instruction" EXTRACTPS $-1, X2, (BX) // ERROR "invalid instruction" // VSIB addressing does not permit non-vector (X/Y)
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Jun 14 00:03:57 GMT 2023 - 8.9K bytes - Viewed (0)