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Results 21 - 30 of 510 for aligned (0.17 sec)
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src/runtime/runtime_mmap_test.go
} } func TestPhysPageSize(t *testing.T) { // Mmap fails if the address is not page aligned, so we can // use this to test if the page size is the true page size. ps := runtime.GetPhysPageSize() // Get a region of memory to play with. This should be page-aligned. b, err := runtime.Mmap(nil, 2*ps, 0, runtime.MAP_ANON|runtime.MAP_PRIVATE, -1, 0) if err != 0 { t.Fatalf("Mmap: %v", err) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 29 16:24:51 UTC 2022 - 1.8K bytes - Viewed (0) -
src/runtime/align_test.go
// type the selector arg on some platforms. return } if p, ok := t.(*types.Pointer); ok { // Note: we assume here that the pointer p in p.foo is properly // aligned. We just check that foo is at a properly aligned offset. t = p.Elem() } else { v.checkAddr(n.X) } if t.Underlying() == t { v.t.Errorf("analysis can't handle unnamed type %s %v", v.fset.Position(n.Pos()), t) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Feb 08 14:52:12 UTC 2023 - 5.4K bytes - Viewed (0) -
src/runtime/mpagealloc_64bit.go
// // The base address of the backing store is always page-aligned, // because it comes from the OS, so it's sufficient to align the // index. haveMin := s.min.Load() haveMax := s.max.Load() needMin := alignDown(uintptr(chunkIndex(base)), physPageSize/scSize) needMax := alignUp(uintptr(chunkIndex(limit)), physPageSize/scSize)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Jan 03 11:00:10 UTC 2024 - 9.3K bytes - Viewed (0) -
src/internal/bytealg/indexbyte_s390x.s
MOVD R8, 0(R2) RET notfoundr0: XOR R0, R0 // reset R0 MOVD $-1, 0(R2) RET vectorimpl: //if the address is not 16byte aligned, use loop for the header MOVD R3, R8 AND $15, R8 CMPBGT R8, $0, notaligned aligned: ADD R6, R4, R8 MOVD R8, R7 AND $-16, R7 // replicate c across V17 VLVGB $0, R5, V19 VREPB $0, V19, V17 vectorloop: CMPBGE R3, R7, residual
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Nov 08 20:52:47 UTC 2018 - 2.5K bytes - Viewed (0) -
src/cmd/internal/obj/arm/a.out.go
/* -1 disables use of REGARG */ const ( REGARG = -1 ) const ( REG_R0 = obj.RBaseARM + iota // must be 16-aligned REG_R1 REG_R2 REG_R3 REG_R4 REG_R5 REG_R6 REG_R7 REG_R8 REG_R9 REG_R10 REG_R11 REG_R12 REG_R13 REG_R14 REG_R15 REG_F0 // must be 16-aligned REG_F1 REG_F2 REG_F3 REG_F4 REG_F5 REG_F6 REG_F7 REG_F8 REG_F9 REG_F10
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 05 16:22:12 UTC 2021 - 7K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/doc.go
PCALIGN also changes the function alignment. If a function has one or more PCALIGN directives, its address will be aligned to the same or coarser boundary, which is the maximum of all the alignment values. In the following example, the function Add is aligned with 128 bytes. Examples: TEXT ·Add(SB),$40-16 MOVD $2, R0 PCALIGN $32 MOVD $4, R1 PCALIGN $128 MOVD $8, R2 RET
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Aug 07 00:21:42 UTC 2023 - 9.6K bytes - Viewed (0) -
src/runtime/mpallocbits.go
} // pages64 returns a 64-bit bitmap representing a block of 64 pages aligned // to 64 pages. The returned block of pages is the one containing the i'th // page in this pallocBits. Each bit represents whether the page is in-use. func (b *pallocBits) pages64(i uint) uint64 { return (*pageBits)(b).block64(i) } // allocPages64 allocates a 64-bit block of 64 pages aligned to 64 pages according
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sat May 18 15:13:43 UTC 2024 - 12.5K bytes - Viewed (0) -
internal/ioutil/ioutil.go
// directio.AlignSize is defined as 0 in MacOS causing divide by 0 error. const DirectioAlignSize = 4096 // CopyAligned - copies from reader to writer using the aligned input // buffer, it is expected that input buffer is page aligned to // 4K page boundaries. Without passing aligned buffer may cause // this function to return error. // // This code is similar in spirit to io.Copy but it is only to be
Registered: Sun Jun 16 00:44:34 UTC 2024 - Last Modified: Wed May 22 23:07:14 UTC 2024 - 10.2K bytes - Viewed (0) -
src/internal/bytealg/indexbyte_arm64.s
// Different bytes have different bit masks (i.e: 1, 4, 16, 64) MOVD $0x40100401, R5 VMOV R1, V0.B16 // Work with aligned 32-byte chunks BIC $0x1f, R0, R3 VMOV R5, V5.S4 ANDS $0x1f, R0, R9 AND $0x1f, R2, R10 BEQ loop // Input string is not 32-byte aligned. We calculate the // syndrome value for the aligned 32 bytes block containing // the first bytes and mask off the irrelevant part. VLD1.P (R3), [V1.B16, V2.B16]
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Nov 08 20:52:47 UTC 2018 - 3.3K bytes - Viewed (0) -
src/runtime/memmove_loong64.s
SUBVU R5, R4, R7 AND $7, R7 BNE R7, out // if less than 8 bytes, do byte copying SGTU $8, R6, R7 BNE R7, out // do one byte at a time until 8-aligned AND $7, R4, R8 BEQ R8, words MOVB (R5), R7 ADDV $1, R5 MOVB R7, (R4) ADDV $1, R4 JMP -6(PC) words: // do 8 bytes at a time if there is room ADDV $-7, R9, R6 // R6 is end pointer-7
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 13 15:04:25 UTC 2024 - 1.8K bytes - Viewed (0)