VWSUBUVV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
	VWSUBUVX	V1, V2, V3			// ERROR "expected integer register in rs1 position"
	VWADDVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
	VWADDVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
	VWSUBVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"

	VDIVESD V1, V2, V3                      // 106113cb
	VDIVESQ V1, V2, V3                      // 1061130b
	VDIVESW V1, V2, V3                      // 1061138b
	VDIVEUD V1, V2, V3                      // 106112cb
	VDIVEUQ V1, V2, V3                      // 1061120b
	VDIVEUW V1, V2, V3                      // 1061128b
	VDIVSD V1, V2, V3                       // 106111cb

	VADDUHM V1, V2, V3              // 10611040
	VADDUWM V1, V2, V3              // 10611080
	VADDUDM V1, V2, V3              // 106110c0
	VADDUQM V1, V2, V3              // 10611100
	VADDCUQ V1, V2, V3              // 10611140
	VADDCUW V1, V2, V3              // 10611180
	VADDUBS V1, V2, V3              // 10611200
	VADDUHS V1, V2, V3              // 10611240
	VADDUWS V1, V2, V3              // 10611280

                    }
                    project(":v2") {
                        version = "2.0"
                    }
                """
            )
            withDirectory("v1/src/main").v1()
            withDirectory("v2/src/main").v2()
            val sourceRoots = if (File(withDirectory("v2/src/main"), "java").exists()) {
                "v2/src/main/java"
            } else {

        graph.setEntry(v1);
        v2 = graph.addVertex(new ArtifactMetadata("g", "a2", "1.0"));
        v3 = graph.addVertex(new ArtifactMetadata("g", "a3", "1.0"));
        v4 = graph.addVertex(new ArtifactMetadata("g", "a4", "1.0"));

        // v1-->v2
        graph.addEdge(v1, v2, new MetadataGraphEdge("1.1", true, null, null, 2, 1));
        graph.addEdge(v1, v2, new MetadataGraphEdge("1.2", true, null, null, 2, 2));

	VZEXTVF4	V2, V3, V4			// ERROR "invalid vector mask register"
	VSEXTVF4	V2, V3, V4			// ERROR "invalid vector mask register"
	VZEXTVF8	V2, V3, V4			// ERROR "invalid vector mask register"
	VSEXTVF8	V2, V3, V4			// ERROR "invalid vector mask register"
	VADCVVM		V1, V2, V4, V3			// ERROR "invalid vector mask register"
	VADCVVM		V1, V2, V3			// ERROR "invalid vector mask register"

	VADDVI		$-16, V2, V3			// d7312802
	VADDVI		$-16, V2, V0, V3		// d7312800
	VSUBVV		V1, V2, V3			// d781200a
	VSUBVV		V1, V2, V0, V3			// d7812008
	VSUBVX		X10, V2, V3			// d741250a
	VSUBVX		X10, V2, V0, V3			// d7412508
	VRSUBVX		X10, V2, V3			// d741250e
	VRSUBVX		X10, V2, V0, V3			// d741250c
	VRSUBVI		$15, V2, V0, V3			// d7b1270c
	VRSUBVI		$-16, V2, V0, V3		// d731280c
	VNEGV		V2, V3				// d741200e

	VXORV		V1, V2, V3      // 43042771
	VNORV		V1, V2, V3      // 43842771
	VANDNV		V1, V2, V3      // 43042871
	VORNV		V1, V2, V3      // 43842871
	VANDV		V1, V2		// 42042671
	VORV		V1, V2		// 42842671
	VXORV		V1, V2		// 42042771
	VNORV		V1, V2		// 42842771
	VANDNV		V1, V2		// 42042871
	VORNV		V1, V2		// 42842871

	// VANDB,VORB,VXORB,VNORB
	VANDB		$0, V2, V3      // 4300d073
	VORB		$64, V2, V3     // 4300d573

pkg math/rand/v2, func Uint32() uint32 #61716
pkg math/rand/v2, func Uint32N(uint32) uint32 #61716
pkg math/rand/v2, func Uint64() uint64 #61716
pkg math/rand/v2, func Uint64N(uint64) uint64 #61716
pkg math/rand/v2, func UintN(uint) uint #61716
pkg math/rand/v2, method (*ChaCha8) MarshalBinary() ([]uint8, error) #61716
pkg math/rand/v2, method (*ChaCha8) Seed([32]uint8) #61716
pkg math/rand/v2, method (*ChaCha8) Uint64() uint64 #61716

- MinIO exports Prometheus compatible data by default as an authorized endpoint at `/minio/v2/metrics/cluster`. 
- MinIO exports Prometheus compatible data by default which is bucket centric as an authorized endpoint at `/minio/v2/metrics/bucket`.
- MinIO exports Prometheus compatible data by default which is node centric as an authorized endpoint at `/minio/v2/metrics/node`.