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Results 11 - 20 of 22 for srw (0.03 sec)
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src/cmd/asm/internal/asm/testdata/s390x.s
XORW -1(R1), R2 // e3201fffff57 // shift and rotate instructions SRD $4, R4, R7 // eb740004000c SRD R1, R4, R7 // eb741000000c SRW $4, R4, R7 // eb74000400de SRW R1, R4, R7 // eb74100000de SLW $4, R3, R6 // eb63000400df SLW R2, R3, R6 // eb63200000df SLD $4, R3, R6 // eb630004000d
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Nov 22 03:55:32 UTC 2023 - 21.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewrite.go
// or return 0 if they cannot be combined. func mergePPC64SldiSrw(sld, srw int64) int64 { if sld > srw || srw >= 32 { return 0 } mask_r := uint32(0xFFFFFFFF) >> uint(srw) mask_l := uint32(0xFFFFFFFF) >> uint(sld) mask := (mask_r & mask_l) << uint(sld) return encodePPC64RotateMask((32-srw+sld)&31, int64(mask), 32) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 64.2K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go
case FADDCC, FADDSCC, FSUBCC, FMULCC, FDIVCC, FDIVSCC: return true case OR, ORCC, ORC, ORCCC, AND, ANDCC, ANDC, ANDCCC, XOR, XORCC, NAND, NANDCC, EQV, EQVCC, NOR, NORCC: return true case SLW, SLWCC, SLD, SLDCC, SRW, SRAW, SRWCC, SRAWCC, SRD, SRDCC, SRAD, SRADCC: return true } return false } // revCondMap maps a conditional register bit to its inverse, if possible. var revCondMap = map[string]string{
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 22 17:16:14 UTC 2022 - 10.9K bytes - Viewed (0) -
src/math/erf_s390x.s
FMOVD 352(R5), F3 WFMADB V2, V0, V5, V0 WFMADB V2, V1, V3, V2 WFMADB V4, V0, V2, V0 WFMADB V6, V0, V6, V0 L1: FMOVD F0, ret+8(FP) RET L2: MOVH R1, R1 MOVH $16407, R3 SRW $31, R1, R1 MOVW R2, R6 MOVW R3, R7 CMPBLE R6, R7, L6 MOVW R1, R1 SLD $3, R1, R1 MOVD $·erftab12067<>+0(SB), R3 WORD $0x68013000 //ld %f0,0(%r1,%r3) MOVH $32751, R1 MOVW R1, R7
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 16 15:34:41 UTC 2019 - 8.5K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64Ops.go
{name: "SRAW", argLength: 2, reg: gp21cxer, asm: "SRAW"}, // signed arg0 >> (arg1&63), 32 bit width {name: "SRD", argLength: 2, reg: gp21, asm: "SRD"}, // unsigned arg0 >> (arg1&127), 64 bit width {name: "SRW", argLength: 2, reg: gp21, asm: "SRW"}, // unsigned arg0 >> (arg1&63), 32 bit width {name: "SLD", argLength: 2, reg: gp21, asm: "SLD"}, // arg0 << (arg1&127), 64 bit width
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 43.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/S390XOps.go
{name: "SRW", argLength: 2, reg: sh21, asm: "SRW"}, // unsigned uint32(arg0) >> arg1, shift amount is mod 64 {name: "SRDconst", argLength: 1, reg: gp11, asm: "SRD", aux: "UInt8"}, // unsigned arg0 >> auxint, shift amount 0-63 {name: "SRWconst", argLength: 1, reg: gp11, asm: "SRW", aux: "UInt8"}, // unsigned uint32(arg0) >> auxint, shift amount 0-31
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 24 00:21:13 UTC 2023 - 52.5K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/doc.go
Examples: SRAD $8,R3,R4 => sradi r4,r3,8 SRD $8,R3,R4 => rldicl r4,r3,56,8 SLD $8,R3,R4 => rldicr r4,r3,8,55 SRAW $16,R4,R5 => srawi r5,r4,16 SRW $40,R4,R5 => rlwinm r5,r4,0,0,31 SLW $12,R4,R5 => rlwinm r5,r4,12,0,19 Some non-simple shifts have operands in the Go assembly which don't map directly
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Apr 21 16:47:45 UTC 2023 - 11.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64.s
SLWCC R3, R4 // 7c841831 SLD $16, R3, R4 // 786483e4 SLD R3, R4, R5 // 7c851836 SLDCC R3, R4 // 7c841837 SRW $8, R3, R4 // 5464c23e SRW R3, R4, R5 // 7c851c30 SRWCC R3, R4 // 7c841c31 SRAW $8, R3, R4 // 7c644670 SRAW R3, R4, R5 // 7c851e30
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 21:53:50 UTC 2024 - 50.2K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 22 17:16:14 UTC 2022 - 334.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewritePPC64.go
// match: (Rsh32Ux16 x y) // cond: shiftIsBounded(v) // result: (SRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRW) v.AddArg2(x, y) return true } // match: (Rsh32Ux16 <t> x y) // result: (ISEL [2] (SRW <t> x y) (MOVDconst [0]) (CMPconst [0] (ANDconst [0xFFE0] y))) for { t := v.Type
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 360.2K bytes - Viewed (0)