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Results 11 - 20 of 151 for addU (0.04 sec)
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src/runtime/asm_mipsx.s
NO_LOCAL_POINTERS; \ /* copy arguments to stack */ \ MOVW stackArgs+8(FP), R1; \ MOVW stackArgsSize+12(FP), R2; \ MOVW R29, R3; \ ADDU $4, R3; \ ADDU R3, R2; \ BEQ R3, R2, 6(PC); \ MOVBU (R1), R4; \ ADDU $1, R1; \ MOVBU R4, (R3); \ ADDU $1, R3; \ JMP -5(PC); \ /* call function */ \ MOVW f+4(FP), REGCTXT; \ MOVW (REGCTXT), R4; \ PCDATA $PCDATA_StackMapIndex, $0; \
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 06 11:46:29 UTC 2024 - 26.3K bytes - Viewed (0) -
src/cmd/internal/obj/loong64/anames.go
// Code generated by stringer -i a.out.go -o anames.go -p loong64; DO NOT EDIT. package loong64 import "cmd/internal/obj" var Anames = []string{ obj.A_ARCHSPECIFIC: "ABSD", "ABSF", "ADD", "ADDD", "ADDF", "ADDU", "ADDW", "AND", "BEQ", "BGEZ", "BLEZ", "BGTZ", "BLTZ", "BFPF", "BFPT", "BNE", "BREAK", "CLO", "CLZ", "CMPEQD", "CMPEQF", "CMPGED", "CMPGEF",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 1.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips64.s
// { // outcode(int($1), &$2, 0, &$4); // } ADD R1, R2 // 00411020 ADDU R1, R2 // 00411021 ADDV R1, R2 // 0041102c ADDVU R1, R2 // 0041102d // LADDW imm ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } ADD $4, R1 // 20210004 ADDV $4, R1 // 60210004 ADDU $4, R1 // 24210004 ADDVU $4, R1 // 64210004 ADD $-7193, R24 // 2318e3e7 ADDV $-7193, R24 // 6318e3e7
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 12.4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/loopbce.go
} return uint64(x - y) } // addU returns x+y. Requires that x+y does not overflow an int64. func addU(x int64, y uint64) int64 { if y >= 1<<63 { if x >= 0 { base.Fatalf("addU overflowed %d + %d", x, y) } x += 1<<63 - 1 x += 1 y -= 1 << 63 } if addWillOverflow(x, int64(y)) { base.Fatalf("addU overflowed %d + %d", x, y) } return x + int64(y) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 07 17:37:47 UTC 2023 - 11.8K bytes - Viewed (0) -
src/runtime/sys_linux_mipsx.s
MOVW 8(R29), R5 // nsec // sec is in R3, nsec in R5 // return nsec in R3 MOVW $1000000000, R4 MULU R4, R3 MOVW LO, R3 ADDU R5, R3 SGTU R5, R3, R4 MOVW $ret+0(FP), R6 #ifdef GOARCH_mips MOVW R3, 4(R6) #else MOVW R3, 0(R6) #endif MOVW HI, R3 ADDU R4, R3 #ifdef GOARCH_mips MOVW R3, 0(R6) #else MOVW R3, 4(R6) #endif RET
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Oct 18 20:57:24 UTC 2022 - 9.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPSOps.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 14:43:03 UTC 2023 - 24K bytes - Viewed (0) -
src/internal/runtime/atomic/atomic_mipsx.s
AND R2, R4 SC R4, (R3) // *R3 = R4 BEQ R4, try_and8 SYNC RET // func Or(addr *uint32, v uint32) TEXT ·Or(SB), NOSPLIT, $0-8 MOVW ptr+0(FP), R1 MOVW val+4(FP), R2 SYNC LL (R1), R3 OR R2, R3 SC R3, (R1) BEQ R3, -4(PC) SYNC RET // func And(addr *uint32, v uint32) TEXT ·And(SB), NOSPLIT, $0-8 MOVW ptr+0(FP), R1 MOVW val+4(FP), R2 SYNC
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sat May 11 21:29:34 UTC 2024 - 4.9K bytes - Viewed (0) -
src/internal/runtime/atomic/atomic_loong64.s
DBAR LL (R6), R7 AND R5, R7 SC R7, (R6) BEQ R7, -4(PC) DBAR RET // func Or(addr *uint32, v uint32) TEXT ·Or(SB), NOSPLIT, $0-12 MOVV ptr+0(FP), R4 MOVW val+8(FP), R5 DBAR LL (R4), R6 OR R5, R6 SC R6, (R4) BEQ R6, -4(PC) DBAR RET // func And(addr *uint32, v uint32) TEXT ·And(SB), NOSPLIT, $0-12 MOVV ptr+0(FP), R4 MOVW val+8(FP), R5 DBAR
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 25 19:53:03 UTC 2024 - 6.3K bytes - Viewed (0) -
src/internal/runtime/atomic/atomic_mips64x.s
SYNC LL (R3), R4 AND R2, R4 SC R4, (R3) BEQ R4, -4(PC) SYNC RET // func Or(addr *uint32, v uint32) TEXT ·Or(SB), NOSPLIT, $0-12 MOVV ptr+0(FP), R1 MOVW val+8(FP), R2 SYNC LL (R1), R3 OR R2, R3 SC R3, (R1) BEQ R3, -4(PC) SYNC RET // func And(addr *uint32, v uint32) TEXT ·And(SB), NOSPLIT, $0-12 MOVV ptr+0(FP), R1 MOVW val+8(FP), R2 SYNC
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sat May 11 21:29:34 UTC 2024 - 7.2K bytes - Viewed (0) -
src/crypto/internal/nistec/p256_asm_ppc64le.s
VMULT_ADD(X1, YDIG, ADD2H, ONE, ADD4, ADD4H) LXVD2X (R17)(CPOOL), SEL1 VSPLTISB $0, ZER // VZERO ZER VPERM ZER, ADD1, SEL1, RED3 // [d0 0 0 d0] VSLDOI $12, ADD2, ADD1, T0 // ADD1 Free // VSLDB VSLDOI $12, ZER, ADD2, T1 // ADD2 Free // VSLDB VADDCUQ T0, ADD3, CAR1 // VACCQ VADDUQM T0, ADD3, T0 // ADD3 Free // VAQ VADDECUQ T1, ADD4, CAR1, T2 // VACCCQ
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 56.5K bytes - Viewed (0)