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Results 1 - 10 of 11 for REGSB (0.05 sec)
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src/cmd/internal/obj/mips/asm0.go
{AMOVW, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64, 0}, {AMOVWU, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64, 0}, {AMOVV, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64, 0}, {AMOVB, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64, 0}, {AMOVBU, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64, 0}, {AMOVWL, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64, 0},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 16 17:46:09 UTC 2024 - 53.6K bytes - Viewed (0) -
src/runtime/rt0_openbsd_mips64.s
#else MOVW 0(R29), R4 // argc #endif ADDV $8, R29, R5 // argv JMP main(SB) TEXT main(SB),NOSPLIT|NOFRAME,$0 // in external linking, glibc jumps to main with argc in R4 // and argv in R5 // initialize REGSB = PC&0xffffffff00000000 BGEZAL R0, 1(PC) SRLV $32, R31, RSB SLLV $32, RSB MOVV $runtime·rt0_go(SB), R1
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 29 08:07:46 UTC 2020 - 976 bytes - Viewed (0) -
src/runtime/rt0_linux_mips64x.s
#else MOVW 0(R29), R4 // argc #endif ADDV $8, R29, R5 // argv JMP main(SB) TEXT main(SB),NOSPLIT|NOFRAME,$0 // in external linking, glibc jumps to main with argc in R4 // and argv in R5 // initialize REGSB = PC&0xffffffff00000000 BGEZAL R0, 1(PC) SRLV $32, R31, RSB SLLV $32, RSB MOVV $runtime·rt0_go(SB), R1
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sat Nov 06 10:24:44 UTC 2021 - 1014 bytes - Viewed (0) -
src/cmd/internal/obj/mips/obj0.go
m := uint32(ANYMEM) if cls == REGSB { m = E_MEMSB } if cls == REGSP { m = E_MEMSP } if ar != 0 { s.used.cc |= m } else { s.set.cc |= m } case C_SACON, C_LACON: s.used.ireg |= 1 << (REGSP - REG_R0) case C_SECON, C_LECON: s.used.ireg |= 1 << (REGSB - REG_R0) case C_REG: if ar != 0 {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Apr 21 19:28:53 UTC 2023 - 30.6K bytes - Viewed (0) -
src/cmd/internal/obj/mips/a.out.go
REG_W29 REG_W30 REG_W31 REG_HI REG_LO REG_LAST = REG_LO // the last defined register REG_SPECIAL = REG_M0 REGZERO = REG_R0 /* set to zero */ REGSP = REG_R29 REGSB = REG_R28 REGLINK = REG_R31 REGRET = REG_R1 REGARG = -1 /* -1 disables passing the first argument in register */ REGRT1 = REG_R1 /* reserved for runtime, duffzero and duffcopy */
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 7.6K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/a.out.go
REG_SPR0 = obj.RBasePPC64 + 1024 // first of 1024 registers REG_XER = REG_SPR0 + 1 REG_LR = REG_SPR0 + 8 REG_CTR = REG_SPR0 + 9 REGZERO = REG_R0 /* set to zero */ REGSP = REG_R1 REGSB = REG_R2 REGRET = REG_R3 REGARG = -1 /* -1 disables passing the first argument in register */ REGRT1 = REG_R20 /* reserved for runtime, duffzero and duffcopy */
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 16K bytes - Viewed (0) -
src/runtime/sys_openbsd_mips64.s
MOVW sig+8(FP), R4 MOVV info+16(FP), R5 MOVV ctx+24(FP), R6 MOVV fn+0(FP), R25 // Must use R25, needed for PIC code. CALL (R25) RET TEXT runtime·sigtramp(SB),NOSPLIT|TOPFRAME,$192 // initialize REGSB = PC&0xffffffff00000000 BGEZAL R0, 1(PC) SRLV $32, R31, RSB SLLV $32, RSB // this might be called in external code context, // where g is not set. MOVB runtime·iscgo(SB), R1 BEQ R1, 2(PC)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Jun 06 18:49:01 UTC 2023 - 8.8K bytes - Viewed (0) -
src/runtime/sys_linux_mips64x.s
TEXT runtime·sigfwd(SB),NOSPLIT,$0-32 MOVW sig+8(FP), R4 MOVV info+16(FP), R5 MOVV ctx+24(FP), R6 MOVV fn+0(FP), R25 JAL (R25) RET TEXT runtime·sigtramp(SB),NOSPLIT|TOPFRAME,$64 // initialize REGSB = PC&0xffffffff00000000 BGEZAL R0, 1(PC) SRLV $32, R31, RSB SLLV $32, RSB // this might be called in external code context, // where g is not set. MOVB runtime·iscgo(SB), R1 BEQ R1, 2(PC)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Oct 18 20:57:24 UTC 2022 - 12K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPS64Ops.go
"R14", "R15", "R16", "R17", "R18", "R19", "R20", "R21", "R22", // R23 = REGTMP not used in regalloc "R24", "R25", // R26 reserved by kernel // R27 reserved by kernel // R28 = REGSB not used in regalloc "SP", // aka R29 "g", // aka R30 "R31", // aka REGLINK "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7", "F8", "F9", "F10", "F11", "F12",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 03:36:31 UTC 2023 - 25.5K bytes - Viewed (0) -
src/runtime/asm_mips64x.s
// R20 already saved // R21 already saved. MOVV R22, 160(R29) // R23 is tmp register. MOVV R24, 168(R29) MOVV R25, 176(R29) // R26 is reserved by kernel. // R27 is reserved by kernel. // R28 is REGSB (not modified by Go code). // R29 is SP. // R30 is g. // R31 is LR, which was saved by the prologue. CALL runtime·wbBufFlush(SB) MOVV 8(R29), R20 MOVV 16(R29), R21 MOVV 24(R29), R3
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 06 19:45:59 UTC 2023 - 24.3K bytes - Viewed (0)