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Results 1 - 10 of 28 for ANDconst (0.35 sec)
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src/cmd/compile/internal/ssa/_gen/ARM64.rules
(ANDconst [c] (MOVDconst [d])) => (MOVDconst [c&d]) (ANDconst [c] (ANDconst [d] x)) => (ANDconst [c&d] x) (ANDconst [c] (MOVWUreg x)) => (ANDconst [c&(1<<32-1)] x) (ANDconst [c] (MOVHUreg x)) => (ANDconst [c&(1<<16-1)] x) (ANDconst [c] (MOVBUreg x)) => (ANDconst [c&(1<<8-1)] x) (MOVWUreg (ANDconst [c] x)) => (ANDconst [c&(1<<32-1)] x) (MOVHUreg (ANDconst [c] x)) => (ANDconst [c&(1<<16-1)] x)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 113.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64.rules
(AND x (MOVDconst [c])) && isU16Bit(c) => (ANDconst [c] x) (XOR x (MOVDconst [c])) && isU32Bit(c) => (XORconst [c] x) (OR x (MOVDconst [c])) && isU32Bit(c) => (ORconst [c] x) // Simplify consts (ANDconst [c] (ANDconst [d] x)) => (ANDconst [c&d] x) (ORconst [c] (ORconst [d] x)) => (ORconst [c|d] x) (XORconst [c] (XORconst [d] x)) => (XORconst [c^d] x) (ANDconst [-1] x) => x (ANDconst [0] _) => (MOVDconst [0]) (XORconst [0] x) => x
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64latelower.rules
(CMPconst [0] z:(ANDconst [c] x)) && int64(uint16(c)) == c && v.Block == z.Block => (CMPconst [0] convertPPC64OpToOpCC(z)) // And finally, fixup the flag user. (CMPconst <t> [0] (Select0 z:((ADD|AND|ANDN|OR|SUB|NOR|XOR)CC x y))) => (Select1 <t> z) (CMPconst <t> [0] (Select0 z:((ADDCCconst|ANDCCconst|NEGCC|CNTLZDCC|RLDICLCC) y))) => (Select1 <t> z)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 3.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPS.rules
// fold extensions and ANDs together (MOVBUreg (ANDconst [c] x)) => (ANDconst [c&0xff] x) (MOVHUreg (ANDconst [c] x)) => (ANDconst [c&0xffff] x) (MOVBreg (ANDconst [c] x)) && c & 0x80 == 0 => (ANDconst [c&0x7f] x) (MOVHreg (ANDconst [c] x)) && c & 0x8000 == 0 => (ANDconst [c&0x7fff] x) // don't extend before store
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 14:43:03 UTC 2023 - 35.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPS64.rules
(Select0 (DIVVU (MOVVconst [c]) (MOVVconst [d]))) && d != 0 => (MOVVconst [int64(uint64(c)%uint64(d))]) // mod (ANDconst [c] (MOVVconst [d])) => (MOVVconst [c&d]) (ANDconst [c] (ANDconst [d] x)) => (ANDconst [c&d] x) (ORconst [c] (MOVVconst [d])) => (MOVVconst [c|d]) (ORconst [c] (ORconst [d] x)) && is32Bit(c|d) => (ORconst [c|d] x) (XORconst [c] (MOVVconst [d])) => (MOVVconst [c^d])
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Jul 31 03:59:48 UTC 2023 - 41.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM.rules
(MOVHUreg x:(MOVHUload _ _)) => (MOVWreg x) // fold extensions and ANDs together (MOVBUreg (ANDconst [c] x)) => (ANDconst [c&0xff] x) (MOVHUreg (ANDconst [c] x)) => (ANDconst [c&0xffff] x) (MOVBreg (ANDconst [c] x)) && c & 0x80 == 0 => (ANDconst [c&0x7f] x) (MOVHreg (ANDconst [c] x)) && c & 0x8000 == 0 => (ANDconst [c&0x7fff] x) // fold double extensions (MOVBreg x:(MOVBreg _)) => (MOVWreg x)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 20 17:19:36 UTC 2023 - 90.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/LOONG64.rules
(REMV (MOVVconst [c]) (MOVVconst [d])) && d != 0 => (MOVVconst [c%d]) // mod (REMVU (MOVVconst [c]) (MOVVconst [d])) && d != 0 => (MOVVconst [int64(uint64(c)%uint64(d))]) // mod (ANDconst [c] (MOVVconst [d])) => (MOVVconst [c&d]) (ANDconst [c] (ANDconst [d] x)) => (ANDconst [c&d] x) (ORconst [c] (MOVVconst [d])) => (MOVVconst [c|d]) (ORconst [c] (ORconst [d] x)) && is32Bit(c|d) => (ORconst [c|d] x) (XORconst [c] (MOVVconst [d])) => (MOVVconst [c^d])
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 19:26:25 UTC 2023 - 31.8K bytes - Viewed (0) -
test/codegen/bitfield.go
func ubfiz7(x uint16) uint64 { return uint64(x << 10) // arm64:"UBFIZ\t[$]10, R[0-9]+, [$]6", } func ubfiz8(x uint8) uint64 { return uint64(x << 7) // arm64:"UBFIZ\t[$]7, R[0-9]+, [$]1", } // merge ANDconst into ubfiz. func ubfiz9(x uint64) uint64 { // arm64:"UBFIZ\t[$]3, R[0-9]+, [$]12",-"LSL",-"AND" // s390x:"RISBGZ\t[$]49, [$]60, [$]3,",-"SLD",-"AND" return (x & 0xfff) << 3 }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 23 06:11:32 UTC 2022 - 9.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewritePPC64.go
return true } // match: (ANDconst [c] (ANDconst [d] x)) // result: (ANDconst [c&d] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpPPC64ANDconst { break } d := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpPPC64ANDconst) v.AuxInt = int64ToAuxInt(c & d) v.AddArg(x) return true } // match: (ANDconst [-1] x) // result: x for {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 360.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64latelower.rules
// These are often the exact inverse of rules in ARM64.rules. (ADDconst [c] x) && !isARM64addcon(c) => (ADD x (MOVDconst [c])) (SUBconst [c] x) && !isARM64addcon(c) => (SUB x (MOVDconst [c])) (ANDconst [c] x) && !isARM64bitcon(uint64(c)) => (AND x (MOVDconst [c])) (ORconst [c] x) && !isARM64bitcon(uint64(c)) => (OR x (MOVDconst [c])) (XORconst [c] x) && !isARM64bitcon(uint64(c)) => (XOR x (MOVDconst [c]))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 4.1K bytes - Viewed (0)