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Results 101 - 110 of 111 for REM (0.16 sec)
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src/cmd/compile/internal/ssa/_gen/ARM64.rules
// In fact, UMOD will be translated into UREM instruction, and UREM is originally translated into // UDIV and MSUB instructions. But if there is already an identical UDIV instruction just before or // after UREM (case like quo, rem := z/y, z%y), then the second UDIV instruction becomes redundant. // The purpose of this rule is to have this extra UDIV instruction removed in CSE pass. (UMOD <typ.UInt64> x y) => (MSUB <typ.UInt64> x y (UDIV <typ.UInt64> x y))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 113.1K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/tools/internal/stdlib/manifest.go
{"Position.Line", Field, 0}, {"Position.Offset", Field, 0}, {"QUO", Const, 0}, {"QUO_ASSIGN", Const, 0}, {"RANGE", Const, 0}, {"RBRACE", Const, 0}, {"RBRACK", Const, 0}, {"REM", Const, 0}, {"REM_ASSIGN", Const, 0}, {"RETURN", Const, 0}, {"RPAREN", Const, 0}, {"SELECT", Const, 0}, {"SEMICOLON", Const, 0}, {"SHL", Const, 0}, {"SHL_ASSIGN", Const, 0},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 02 02:20:05 UTC 2024 - 534.2K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/asm9.go
v := c.regoff(&p.From) & 1 o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.To.Reg)) | uint32(v)<<21 } else { o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.From.Reg)) } case 50: /* rem[u] r1[,r2],r3 */ r := int(p.Reg) if r == 0 { r = int(p.To.Reg) } v := c.oprrr(p.As) t := v & (1<<10 | 1) /* OE|Rc */ o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 13:55:28 UTC 2024 - 156.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteRISCV64.go
v.AddArg2(x, y) return true } return false } func rewriteValueRISCV64_OpMod64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Mod64 x y [false]) // result: (REM x y) for { if auxIntToBool(v.AuxInt) != false { break } x := v_0 y := v_1 v.reset(OpRISCV64REM) v.AddArg2(x, y) return true } return false }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 205.1K bytes - Viewed (0) -
fess-crawler/src/main/resources/org/codelibs/fess/crawler/mime/tika-mimetypes.xml
<alias type="application/bat"/> <sub-class-of type="text/plain"/> <magic priority="50"> <match value="@echo off" type="stringignorecase" offset="0" /> <match value="rem " type="stringignorecase" offset="0" /> </magic> <glob pattern="*.bat"/> <glob pattern="*.cmd"/> </mime-type> <mime-type type="application/batch-smtp"/> <mime-type type="application/beep+xml"/>
Registered: Wed Jun 12 15:17:51 UTC 2024 - Last Modified: Thu Sep 21 06:46:43 UTC 2023 - 298.5K bytes - Viewed (0) -
src/regexp/testdata/re2-exhaustive.txt.bz2
`�� ʙ���P i�@Y`(�� � P V�@�H P P(V����\r�� �����`�i����2b 6�UH� oR��z�1 `�` $�IP��@ � 5*��ʪ� h IE4M*� ������$������I3��7.[��lJtc>㻒���.庉��N\�N�w�k�ts��_9�;V�j�j懽%�j���懏9[�������zϧ�ի�r~m��"�=REm�bN�ϱ�� � ���u���{j6��>��Dy�rC���m��"���O��w�cڟ@�E��x|â�25������^�r z�C�RK�J#��kF�گ�k�Z��V�l£Z�X h E�F���(Z�P ( o� i������AWx�;�l.�Z��p� 0�`��� T�� b4�hH��ղ�m5� ����_O�c���x~�Ç�t����kVZ�χgggavu|��5�M��'�)O�T���ǷT�zg��������...
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 13 14:52:20 UTC 2021 - 418.2K bytes - Viewed (0) -
samples/bookinfo/src/productpage/static/tailwind/tailwind.css
);is();ns();St();Db=["min","max","clamp","calc"];Ib=new Set(["scroll-timeline-name","timeline-scope","view-timeline-name","font-palette","scroll-timeline","animation-timeline","view-timeline"]);Rb=["cm","mm","Q","in","pc","pt","px","em","ex","ch","rem","lh","rlh","vw","vh","vmin","vmax","vb","vi","svw","svh","lvw","lvh","dvw","dvh","cqw","cqh","cqi","cqb","cqmin","cqmax"],Mb=`(?:${Rb.join("|")})`;Bb=new Set(["thin","medium","thick"]);Fb=new Set(["conic-gradient","linear-gradient","radial-gradien...
Registered: Fri Jun 14 15:00:06 UTC 2024 - Last Modified: Tue May 28 14:48:01 UTC 2024 - 357.1K bytes - Viewed (1) -
api/go1.14.txt
pkg hash/maphash, type Hash struct pkg hash/maphash, type Seed struct pkg log, const Lmsgprefix = 64 pkg log, const Lmsgprefix ideal-int pkg math, func FMA(float64, float64, float64) float64 pkg math/bits, func Rem(uint, uint, uint) uint pkg math/bits, func Rem32(uint32, uint32, uint32) uint32 pkg math/bits, func Rem64(uint64, uint64, uint64) uint64 pkg mime/multipart, method (*Reader) NextRawPart() (*Part, error)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 17 20:31:46 UTC 2023 - 508.9K bytes - Viewed (0) -
api/go1.txt
pkg go/token, const QUO Token pkg go/token, const QUO_ASSIGN Token pkg go/token, const RANGE Token pkg go/token, const RBRACE Token pkg go/token, const RBRACK Token pkg go/token, const REM Token pkg go/token, const REM_ASSIGN Token pkg go/token, const RETURN Token pkg go/token, const RPAREN Token pkg go/token, const SELECT Token pkg go/token, const SEMICOLON Token pkg go/token, const SHL Token
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Aug 14 18:58:28 UTC 2013 - 1.7M bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
}, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "REM", argLen: 2, asm: riscv.AREM, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)