if r == 0 {
		return "NONE"
	}
	if r == REGG {
		// Special case.
		return "g"
	}
	if REG_R0 <= r && r <= REG_R31 {
		return fmt.Sprintf("R%d", r-REG_R0)
	}
	if REG_F0 <= r && r <= REG_F31 {
		return fmt.Sprintf("F%d", r-REG_F0)
	}
	if REG_FCSR0 <= r && r <= REG_FCSR31 {
		return fmt.Sprintf("FCSR%d", r-REG_FCSR0)
	}
	if REG_FCC0 <= r && r <= REG_FCC31 {
		return fmt.Sprintf("FCC%d", r-REG_FCC0)
	}

func sizeExtRelocs(ctxt *Link, relsize uint32) {
	if relsize == 0 {
		panic("sizeExtRelocs: relocation size not set")
	}
	var sz int64
	for _, seg := range Segments {
		for _, sect := range seg.Sections {
			sect.Reloff = uint64(ctxt.Out.Offset() + sz)
			sect.Rellen = uint64(relsize * sect.Relcount)
			sz += int64(sect.Rellen)
		}
	}
	filesz := ctxt.Out.Offset() + sz
	err := ctxt.Out.Mmap(uint64(filesz))
	if err != nil {

				sh.Name = cstring(sh32.Name[0:])
				sh.Seg = cstring(sh32.Seg[0:])
				sh.Addr = uint64(sh32.Addr)
				sh.Size = uint64(sh32.Size)
				sh.Offset = sh32.Offset
				sh.Align = sh32.Align
				sh.Reloff = sh32.Reloff
				sh.Nreloc = sh32.Nreloc
				sh.Flags = sh32.Flags
				if err := f.pushSection(sh, r); err != nil {
					return nil, err
				}
			}

		case LoadCmdSegment64:
			var seg64 Segment64

		{regAddr(REG_DH), Yrb},
		{regAddr(REG_BH), Yrb},
		{regAddr(REG_CL), Ycl},
		{regAddr(REG_CX), Ycx},
		{regAddr(REG_DX), Yrx},
		{regAddr(REG_BX), Yrx},
		{regAddr(REG_F0), Yf0},
		{regAddr(REG_F3), Yrf},
		{regAddr(REG_F7), Yrf},
		{regAddr(REG_M0), Ymr},
		{regAddr(REG_M3), Ymr},
		{regAddr(REG_M7), Ymr},
		{regAddr(REG_X0), Yxr0},
		{regAddr(REG_X6), Yxr},
		{regAddr(REG_X13), Yxr},

	Sections []*Section
}

type Section struct {
	Rwx     uint8
	Extnum  int16
	Align   int32
	Name    string
	Vaddr   uint64
	Length  uint64
	Seg     *Segment
	Elfsect interface{} // an *ld.ElfShdr
	Reloff  uint64
	Rellen  uint64
	// Relcount is the number of *host* relocations applied to this section
	// (when external linking).
	// Incremented atomically on multiple goroutines.

	if r == 0 {
		return "NONE"
	}
	if r == REGG {
		// Special case.
		return "g"
	}
	if REG_R0 <= r && r <= REG_R31 {
		return fmt.Sprintf("R%d", r-REG_R0)
	}
	if REG_F0 <= r && r <= REG_F31 {
		return fmt.Sprintf("F%d", r-REG_F0)
	}
	if REG_V0 <= r && r <= REG_V31 {
		return fmt.Sprintf("V%d", r-REG_V0)
	}
	if REG_VS0 <= r && r <= REG_VS63 {
		return fmt.Sprintf("VS%d", r-REG_VS0)
	}

					//
					// [For future reference, see Darwin's /usr/include/mach-o/x86_64/reloc.h]
					secaddr := c.seg.sect[rel.symnum-1].addr
					rAdd = int64(uint64(int64(int32(e.Uint32(p[rOff:])))+int64(rOff)+4) - secaddr)
				} else {
					rAdd = int64(int32(e.Uint32(p[rOff:])))
				}
			}

			// An unsigned internal relocation has a value offset
			// by the section address.

		panic(fmt.Sprintf("invalid or unknown event %s", name))
	}
	var uintArgs []uint64
	argOff := 0
	if b.gen.trace.specs[ev].IsTimedEvent {
		if b.gen.trace.validTimestamps {
			uintArgs = []uint64{1}
		} else {
			uintArgs = []uint64{0}
		}
		argOff = 1
	}
	spec := b.gen.trace.specs[ev]
	if arity := len(spec.Args) - argOff; len(args) != arity {

			continue
		}
		if i == riscv.REG_TP || i == riscv.REG_G {
			continue
		}
		name := fmt.Sprintf("X%d", i-riscv.REG_X0)
		register[name] = int16(i)
	}
	for i := riscv.REG_F0; i <= riscv.REG_F31; i++ {
		name := fmt.Sprintf("F%d", i-riscv.REG_F0)
		register[name] = int16(i)
	}

	// General registers with ABI names.
	register["ZERO"] = riscv.REG_ZERO
	register["RA"] = riscv.REG_RA
	register["SP"] = riscv.REG_SP

	return ValAndOff(int64(val)<<32 + int64(uint32(off)))
}

func (x ValAndOff) canAdd32(off int32) bool {
	newoff := x.Off64() + int64(off)
	return newoff == int64(int32(newoff))
}
func (x ValAndOff) canAdd64(off int64) bool {
	newoff := x.Off64() + off
	return newoff == int64(int32(newoff))
}

func (x ValAndOff) addOffset32(off int32) ValAndOff {
	if !x.canAdd32(off) {