//
	// We apply this rewrite on systems that support the 1-instruction form.
	// The decision is made using only the operating system and the -shared flag,
	// not the link mode. If some link modes on a particular operating system
	// require the 2-instruction form, then all builds for that operating system
	// will use the 2-instruction form, so that the link mode decision can be
	// delayed to link time.
	//

	OP_ADDIS         = 0x3c000000 // addis
	OP_LD            = 0xe8000000 // ld
	OP_PLA_PFX       = 0x06100000 // pla (prefix instruction word)
	OP_PLA_SFX       = 0x38000000 // pla (suffix instruction word)
	OP_PLD_PFX_PCREL = 0x04100000 // pld (prefix instruction word, R=1)
	OP_PLD_SFX       = 0xe4000000 // pld (suffix instruction word)
	OP_MFLR          = 0x7c0802a6 // mflr
	OP_MTLR          = 0x7c0803a6 // mtlr
	OP_MFCTR         = 0x7c0902a6 // mfctr

     * <a href="http://www.eclemma.org/jacoco/trunk/doc/api/org/jacoco/core/analysis/ICoverageNode.CounterEntity.html">org.jacoco.core.analysis.ICoverageNode.CounterEntity</a>.
     * Valid values are INSTRUCTION, LINE, BRANCH, COMPLEXITY, METHOD and CLASS. Defaults to INSTRUCTION.
     */
    @Input
    String getCounter();

    /**
     * Sets the counter that applies to the limit.
     *
     * @param counter Counter
     */

	var l = layout{sp: "R15", stack: 16} // add slot to save PC of interrupted instruction and flags
	l.addSpecial(
		"STMG R0, R12, %d(R15)",
		"LMG %d(R15), R0, R12",
		13*8)
	// Add floating point registers F0-F31.
	for i := 0; i <= 15; i++ {
		reg := fmt.Sprintf("F%d", i)
		l.add("FMOVD", reg, 8)
	}

	// allocate frame, save PC of interrupted instruction (in LR) and flags (condition code)

//   - series of calls to b.Live/b.Kill based on a backwards reverse layout
//     order scan over instructions
//   - invoke b.Finish() to produce final set
//
// See the Live method comment for an IR example.
type IntervalsBuilder struct {
	s Intervals
	// index of last instruction visited plus 1
	lidx int
}

func (c *IntervalsBuilder) last() int {
	return c.lidx - 1
}

// license that can be found in the LICENSE file.

// These tests check that atomic instructions without dynamic checks are
// generated for architectures that support them

package codegen

import "sync/atomic"

type Counter struct {
	count int32
}

func (c *Counter) Increment() {
	// Check that ARm64 v8.0 has both atomic instruction (LDADDALW) and a dynamic check

	}

	// HWCAP feature bits
	ARM.HasVFPv4 = isSet(HWCap, hwcap_VFPv4)
	ARM.HasIDIVA = isSet(HWCap, hwcap_IDIVA)
	// lpae is required to make the 64-bit instructions LDRD and STRD (and variants) atomic.
	// See ARMv7 manual section B1.6.
	// We also need at least a v7 chip, for the DMB instruction.
	ARM.HasV7Atomics = isSet(HWCap, hwcap_LPAE) && isV7(Platform)
}

func isSet(hwc uint, value uint) bool {
	return hwc&value != 0
}

// See comments in ARM64latelower.rules...

	// NOT pseudo-instruction
	NOT	X5					// 93c2f2ff
	NOT	X5, X6					// 13c3f2ff

	// NEG/NEGW pseudo-instructions
	NEG	X5					// b3025040
	NEG	X5, X6					// 33035040
	NEGW	X5					// bb025040
	NEGW	X5, X6					// 3b035040

	// This jumps to the second instruction in the function (the
	// first instruction is an invisible stack pointer adjustment).
	JMP	start					// JMP	2

class JacocoLimitImplTest extends Specification {

    JacocoLimitImpl limit = new JacocoLimitImpl()

    def "provides expected default field values"() {
        expect:
        limit.counter == 'INSTRUCTION'
        limit.value == 'COVEREDRATIO'
        !limit.minimum
        !limit.maximum
    }