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Results 61 - 69 of 69 for Uint16 (0.04 sec)
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src/cmd/asm/internal/arch/s390x.go
"CRJ", "CGRJ", "CLRJ", "CLGRJ", "CIJ", "CGIJ", "CLIJ", "CLGIJ", "CALL", "JMP": return true } return false } func s390xRegisterNumber(name string, n int16) (int16, bool) { switch name { case "AR": if 0 <= n && n <= 15 { return s390x.REG_AR0 + n, true } case "F": if 0 <= n && n <= 15 { return s390x.REG_F0 + n, true } case "R":
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Thu Oct 17 14:55:25 UTC 2019 - 1.2K bytes - Viewed (0) -
src/cmd/asm/internal/arch/loong64.go
"B32": loong64.ARNG_32B, "H16": loong64.ARNG_16H, "W8": loong64.ARNG_8W, "V4": loong64.ARNG_4V, "Q2": loong64.ARNG_2Q, } // Loong64RegisterExtension constructs an Loong64 register with extension or arrangement. func Loong64RegisterExtension(a *obj.Addr, ext string, reg, num int16, isAmount, isIndex bool) error { var ok bool var arng_type int16 var simd_type int16 switch {
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Tue Aug 05 17:31:25 UTC 2025 - 3.8K bytes - Viewed (0) -
src/cmd/asm/internal/arch/mips.go
mips.ADIV, mips.ADIVU, mips.ADIVV, mips.ADIVVU, mips.AREM, mips.AREMU, mips.AREMV, mips.AREMVU, mips.AMADD, mips.AMSUB: return true } return false } func mipsRegisterNumber(name string, n int16) (int16, bool) { switch name { case "F": if 0 <= n && n <= 31 { return mips.REG_F0 + n, true } case "FCR": if 0 <= n && n <= 31 { return mips.REG_FCR0 + n, true } case "M":
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed Mar 04 19:06:44 UTC 2020 - 1.7K bytes - Viewed (0) -
src/cmd/asm/internal/arch/ppc64.go
ppc64.ASUBME, ppc64.ASUBZECC, ppc64.ASUBZEVCC, ppc64.ASUBZEV, ppc64.ASUBZE: return true } return false } func ppc64RegisterNumber(name string, n int16) (int16, bool) { switch name { case "CR": if 0 <= n && n <= 7 { return ppc64.REG_CR0 + n, true } case "A": if 0 <= n && n <= 8 { return ppc64.REG_A0 + n, true } case "VS":
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Thu Nov 21 18:27:17 UTC 2024 - 2.3K bytes - Viewed (0) -
src/cmd/asm/internal/arch/arm.go
} if b, present := scond[name]; present { bits = (bits &^ arm.C_SCOND) | b continue } return 0, false } return bits, true } func armRegisterNumber(name string, n int16) (int16, bool) { if n < 0 || 15 < n { return 0, false } switch name { case "R": return arm.REG_R0 + n, true case "F": return arm.REG_F0 + n, true } return 0, false
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed Oct 23 15:18:14 UTC 2024 - 6.1K bytes - Viewed (0) -
api/go1.17.txt
pkg database/sql, type NullByte struct pkg database/sql, type NullByte struct, Byte uint8 pkg database/sql, type NullByte struct, Valid bool pkg database/sql, type NullInt16 struct pkg database/sql, type NullInt16 struct, Int16 int16 pkg database/sql, type NullInt16 struct, Valid bool pkg debug/elf, const SHT_MIPS_ABIFLAGS = 1879048234 pkg debug/elf, const SHT_MIPS_ABIFLAGS SectionType pkg encoding/csv, method (*Reader) FieldPos(int) (int, int)
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Fri Feb 17 20:31:46 UTC 2023 - 18K bytes - Viewed (0) -
src/cmd/asm/internal/asm/asm.go
} return addr.Offset } // getRegister checks that addr represents a register and returns its value. func (p *Parser) getRegister(prog *obj.Prog, op obj.As, addr *obj.Addr) int16 { if addr.Type != obj.TYPE_REG || addr.Offset != 0 || addr.Name != 0 || addr.Index != 0 { p.errorf("%s: expected register; found %s", op, obj.Dconv(prog, addr)) } return addr.Reg }
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Tue Aug 05 17:31:25 UTC 2025 - 26.2K bytes - Viewed (0) -
android/guava/src/com/google/common/hash/Crc32cHashFunction.java
/* * This trick allows us to avoid having separate states for "first four ints" and "all other * four int chunks." The state we want after the first four bytes is * * crc0 = ~int0 * crc1 = int1 * crc2 = int2 * crc3 = int3 * * ...so we set crc0 so that computeForWord(crc0) = -1 and xoring it with the first int
Registered: Fri Sep 05 12:43:10 UTC 2025 - Last Modified: Sat Dec 28 01:26:26 UTC 2024 - 21.2K bytes - Viewed (0) -
RELEASE.md
* Added 16-bit and 32-bit int support for the built-in op `bitcast`. * Added 8-bit/16-bit/32-bit int/uint support for the built-in op `bitwise_xor` * Added int16 indices support for built-in op `gather` and `gather_nd`. * Added 8-bit/16-bit/32-bit int/uint support for the built-in op `right_shift` * Added reference implementation for 16-bit int unquantized `add`.
Registered: Tue Sep 09 12:39:10 UTC 2025 - Last Modified: Mon Aug 18 20:54:38 UTC 2025 - 740K bytes - Viewed (2)