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Results 31 - 40 of 40 for bfi1 (0.09 sec)
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src/os/os_test.go
if err != nil { t.Fatalf("StartProcess: %v", err) } w.Close() var b strings.Builder io.Copy(&b, r) output := b.String() fi1, _ := Stat(strings.TrimSpace(output)) fi2, _ := Stat(expect) if !SameFile(fi1, fi2) { t.Errorf("exec %q returned %q wanted %q", strings.Join(append([]string{cmd}, args...), " "), output, expect) } p.Wait() } }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 01:00:11 UTC 2024 - 83.1K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/inst.json
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Aug 16 17:57:48 UTC 2017 - 234.7K bytes - Viewed (0) -
src/runtime/asm_amd64.s
#define V3_FEATURES_CX (V2_FEATURES_CX | 1 << 12 | 1 << 22 | 1 << 27 | 1 << 28 | 1 << 29) // ABM (FOR LZNCT) #define V3_EXT_FEATURES_CX (V2_EXT_FEATURES_CX | 1 << 5) // BMI1 AVX2 BMI2 #define V3_EXT_FEATURES_BX (1 << 3 | 1 << 5 | 1 << 8) // XMM YMM #define V3_OS_SUPPORT_AX (1 << 1 | 1 << 2) #define V4_FEATURES_CX V3_FEATURES_CX
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sat May 11 20:38:24 UTC 2024 - 60.4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
{name: "PrefetchT0", argLength: 2, reg: prefreg, asm: "PREFETCHT0", hasSideEffects: true}, {name: "PrefetchNTA", argLength: 2, reg: prefreg, asm: "PREFETCHNTA", hasSideEffects: true}, // CPUID feature: BMI1. {name: "ANDNQ", argLength: 2, reg: gp21, asm: "ANDNQ", clobberFlags: true}, // arg0 &^ arg1 {name: "ANDNL", argLength: 2, reg: gp21, asm: "ANDNL", clobberFlags: true}, // arg0 &^ arg1
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Aug 04 16:40:24 UTC 2023 - 98K bytes - Viewed (1) -
src/cmd/compile/internal/ssa/_gen/AMD64.rules
&& clobber(call) => (Move [sz] dst src mem) // Prefetch instructions (PrefetchCache ...) => (PrefetchT0 ...) (PrefetchCacheStreamed ...) => (PrefetchNTA ...) // CPUID feature: BMI1. (AND(Q|L) x (NOT(Q|L) y)) && buildcfg.GOAMD64 >= 3 => (ANDN(Q|L) x y) (AND(Q|L) x (NEG(Q|L) x)) && buildcfg.GOAMD64 >= 3 => (BLSI(Q|L) x)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 93.9K bytes - Viewed (0) -
src/cmd/internal/obj/arm/asm5.go
rf := int(p.From.Reg) rt := int(p.To.Reg) rt2 := int(p.To.Offset) r := int(p.Reg) o1 |= (uint32(rf)&15)<<8 | (uint32(r)&15)<<0 | (uint32(rt)&15)<<16 | (uint32(rt2)&15)<<12 case 18: /* BFX/BFXU/BFC/BFI */ o1 = c.oprrr(p, p.As, int(p.Scond)) rt := int(p.To.Reg) r := int(p.Reg) if r == 0 { r = rt } else if p.As == ABFC { // only "BFC $width, $lsb, Reg" is accepted, p.Reg must be 0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 15 20:51:01 UTC 2023 - 79.4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteARM64.go
v.AddArg2(x0, y) return true } break } // match: (OR (UBFIZ [bfc] x) (ANDconst [ac] y)) // cond: ac == ^((1<<uint(bfc.getARM64BFwidth())-1) << uint(bfc.getARM64BFlsb())) // result: (BFI [bfc] y x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64UBFIZ { continue } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0]
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 608.6K bytes - Viewed (0) -
src/regexp/testdata/re2-exhaustive.txt.bz2
DG$.��� �pu��p �%����R+D��Fتa�������|����h���4msc�9�K���4msc�6���\�据lsF�6=n�t�p�6���\�据lz���.�4msc�5sc�6����捯[ݮ�� �F�69�k�ѵ͏[�]%� la���iJZ�\�ZR�0�����cK,X�""6#b"�12�cc( �Kf�iD�I6PI�d�&Kc5�M���D��IJF$��D��H�5aLj3fi1�6�KV�Z�,U&&X �hĖ ��h �X cF$�jѶ��$��k�"H��HHHHK ն�+3V6I,��ZL$�J$E�J�PV�1[�&f� �Vɤ���4���i���M&���5YM�f�l�ZQ"i�̓I��ijm�j3Vّl�JAiD�m��5m�51��4�bC6�lKfm��V+�Q��;�۪5�Z�;�۪6ѫ��k�[s���\��� @��J��J��Ht�I�֍lkF�5m�GM$� h�6��3u��V ��cILj��a��...
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 13 14:52:20 UTC 2021 - 418.2K bytes - Viewed (0) -
RELEASE.md
Nishant Agrawal, Petr Janda, Yuncheng Li, @raix852, Robert Rose, @Robin-des-Bois, Rohit Girdhar, Sam Abrahams, satok16, Sergey Kishchenko, Sharkd Tu, @shotat, Siddharth Agrawal, Simon Denel, @sono-bfio, SunYeop Lee, Thijs Vogels, @tobegit3hub, @Undo1, Wang Yang, Wenjian Huang, Yaroslav Bulatov, Yuan Tang, Yunfeng Wang, Ziming Dong We are also grateful to all who filed issues or helped resolve them, asked and
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Jun 11 23:24:08 UTC 2024 - 730.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "BFI", auxType: auxARM64BitField, argLen: 2, resultInArg0: true, asm: arm64.ABFI, reg: regInfo{ inputs: []inputInfo{
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)